Greg Miller

An Active Compensator Scheme for Dynamic Voltage Scaling of Voltage Regulators

Dynamic voltage scaling (DVS) technique is a common industry practice in optimizing power consumption of microprocessors by dynamically altering the supply voltage under different operational modes, while maintaining the performance requirements. During DVS operation, it is desirable to position the output voltage to a new level commanded by the microprocessor (CPU) with minimum delay. However, voltage deviation and slow settling time usually exist due to large output capacitance and compensation delay in voltage regulators. Although optimal DVS can be achieved by modifying the output capacitance and compensation, this method is limited by constraints from stringent static and dynamic requirements. In this paper, the effects of output capacitance and compensation network on DVS operation are discussed in detail. An active compensator scheme is then proposed to ensure smooth transition of the output voltage without change of power stage and compensation during DVS. Simulation and experimental results are included to demonstrate the effectiveness of the proposed scheme.

Dual-Edge Pulse Width Modulation Scheme for Fast Transient Response of Multiple-Phase Voltage Regulators

Transient response is a key performance for the multiphase voltage regulator, especially in microprocessor core (Vcore) applications. Conventional PWM modulation schemes have delay times which can increase the demand on the output capacitors, forcing designs to employ more capacitors for acceptable performance. A new modulation scheme is proposed to achieve very fast transient response by dramatically reducing the modulator delay time. The required output capacitors are much less with this scheme, especially in a Vcore multiphase voltage regulator. In this paper, the conventional modulator delay time is investigated and compared with the new scheme, and some experimental results are included to illustrate the impact of the new modulator on transient performance.

Power Loss Analyses for Dynamic Phase Number Control in Multiphase Voltage Regulators

To improve efficiency over a wide load range, it is important to dynamically adjust the operational phase number in multiphase voltage regulators. This paper analyzes in detail the power loss profile of a synchronous multi-phase buck converter and defines the optimal phase number under different load conditions. Experimental results are provided to verify the theoretical results.

Adaptive Modulation Control for Multiple-Phase Voltage Regulators

This paper presents a new Adaptive Modulation Control (AMC) method which has proven to be very effective in achieving high bandwidth designs. AMC is a type of nonlinear control since it works only during large dynamic load transitions. Influence of AMC in both the time domain and frequency domain is analyzed. Simulation results and experimental data are included to show a very high bandwidth as well as excellent transient performance.

Light load efficiency enhancement of a LLC resonant converter

Zero Voltage Switching (ZVS) technique minimizes the turn-on loss of the MOSFETs in LLC resonant converter structure. However, as switching frequency increases, the converter efficiency will suffer due to the increased turn-off loss and gate charge loss, and these effects are especially problematic at light load conditions, where the switching frequency has to be further increased in order to regulate the output. A new hysteretic control scheme is proposed in this paper. By fixing the switching frequency equal to the resonant frequency all the time and skipping pulses proportional to the load condition, the switching losses are reduced and the light load efficiency is improved. The experimental results prove the functionality of the proposed hysteretic control scheme.

Driver deadtime control and its impact on system stability of synchronous buck voltage regulator

Driver dead-time control is a popular scheme used to prevent the occurrence of the shoot-through issue in a synchronous Buck voltage regulator. As the switching frequency is continually increasing in todays converter design, the deadtime interval is now long enough relative to the switching period to impact the system performance. In addition to its impact on efficiency, driver dead-time also impacts loop gain and system stability, especially under the critical load condition. In this paper, the influence of driver dead time on the synchronous buck converter is investigated in detail. With voltage mode control, the system loop gain will change under different load conditions due to the deadtime impact. The deadtime may cause sub-harmonic current ripple in the voltage regulator with sample-and-hold current mode control, while its impact on the peak current mode control can be ignored. Design equations are provided to avoid this issue. Some analysis data are included and compared to experimental results.

Hysteretic control of LLC resonant converter for solar and dc-dc applications

The growing popularity of LLC resonant converter in half-bridge implementation is due to its high efficiency and ability to achieve high power density. Zero Voltage Switching (ZVS) technique minimizes the turn-on loss of the MOSFETs. However, as switching frequency increases, the converter efficiency will suffer due to the increased turn-off loss and gate charge loss. These effects are especially problematic at light load conditions, where the switching frequency has to be further increased in order to regulate the output. A new hysteretic control scheme is proposed in this paper. By fixing the switching frequency equal to the resonant frequency and skipping pulses proportional to the load condition, the switching losses are reduced and the light load efficiency is improved. Moreover, the switching frequency range is limited and therefore wider line and load range can be achieved.

Phase Doubler for high power voltage regulators

As the power consumption of microprocessors increases, a high phase count voltage regulator is required to meet the power hunger (>180A) and high efficiency requirements. In general, the higher the phase number count, the more PWM outputs and current sensing inputs are required for the PWM controller. Developing a very high phase count PWM controller becomes very challenging and requires a high pin count package, resulting in high cost and complex layout design. In this paper, a Phase Doubler, using a single PWM input to drive two interleaved phases, is proposed to overcome these problems. The Phase Doubler can be further expanded to quadruple the phase count, i.e, control 4 phases with only a single PWM input. Some experimental data of a 12-phase voltage regulator are included to verify the concept.

A new active compensator scheme for dynamic voltage scaling in voltage regulators

Dynamic voltage scaling (DVS) techniques are used to optimize the power consumption of the microprocessor by reducing the operating voltage under light-load conditions. To maximize the power saving of DVS, the voltage regulator should adjust the operating voltage to the new voltage commanded by the system as soon as possible. However the voltage regulator output capacitors and the compensation network may impact the voltage transitioning and settling time during DVS operation. In this paper, these impacts are discussed in detail and an active compensator scheme is proposed to optimize the DVS performance. Experimental results are included to illustrate the effectiveness of the proposed scheme.

Single inductor dual output dc-dc converter for space-limited or large input voltage variation systems

The design of a Single Inductor Dual Output (SIDO) buck converter using two individual voltage mode control loops has been presented in this paper, and the limitation of using such control method has been indicated, then the control schemes for minimizing the cross regulation issue has been discussed. By using two separate control loops, the inductor energy is shared and regulated for both output rails. The bench test results show that both outputs of the proposed scheme can achieve good regulation in steady state, and the auxiliary output rail can also obtain good line regulation. The proposed structure is a promising candidate for space-limited applications or for large input voltage variation systems. Furthermore, by using current mode control on the auxiliary output rail, the load cross regulation issue can be reduced.