Greg Unruh

26.6 A 5GS/S 150mW 10b SHA-less pipelined/SAR hybrid ADC in 28nm CMOS

The recent emergence of direct sampling in residential broadband satellite and cable receivers has spurred the need for low-power, high-speed (~5GS/s), mid-resolution (~10b) A/D converters. Recently, time-interleaved (TI) SARs have been a popular choice for low-power, medium-speed, mid-resolution ADCs [1-3]. As the conversion rate and resolution requirements increase, TI-SARs become less attractive in terms of power efficiency and complexity compared to TI-pipelined ADCs [4], where the critical SNR, THD, and TI matching are only required in the MDACs resolving the MSBs. In this paper we report a hybrid of TI-pipelined MDAC and TI-SAR, in which the former resolves the 2 MSB bits and the latter resolves the 8 lower bits. This hybrid architecture combines the advantages from each ADC type to achieve better power at 5GS/s. The front-end is implemented by time-interleaving two 2.5b MDAC slices, easing the timing-matching requirement and complexity. The MDAC stage also eases the timing-matching requirement among the TI-SARs by presenting an amplified-and-held signal to each SAR input. This allows taking advantage of a low-resolution SARs simplicity and low power, for the last 8b. This work also proposes a SHA-less front-end to further minimize the ADC power. Two simple calibration techniques are introduced on-chip to enable the topology: (a) an over-range calibration (ORcal) loop to correct the sampling-time error between MDAC and sub-ADC in the SHA-less front-end, and (b) SAR reference calibration to align the SARs full-scale to the MDACs. Figure 26.6.1 shows the timing and functional block diagram of the 5GS/s hybrid SHA-less ADC. The RF buffer directly drives two TI-slices, each comprising a 2.5GS/S MDAC stage to resolve the 2.5 MSB bits, followed by 4-way interleaved 625MS/S SARs to resolve the lower 8b, for a combined 10b resolution (1b overlap), at 5GS/s.

A 5 GS/s 150 mW 10 b SHA-Less Pipelined/SAR Hybrid ADC for Direct-Sampling Systems in 28 nm CMOS

This paper presents a 28 nm CMOS 10 b SHA-less pipelined/SAR hybrid ADC, designed to enable a direct-sampling receiver system. To achieve low power at 5 GS/s, the ADC combines pipelined and SAR quantizers, powered at 1.8 V and 1 V, respectively. A 2.5 b 2-way time-interleaved 2.5 GS/s multiplying digital-to-analog converter (MDAC) is followed by an 8 b 8-way time-interleaved 625 MHz successive-approximation register (SAR). This architecture combines the benefits of both ADC topologies and allows significant power and complexity reduction. The high-speed 2.5 b MDAC front-end simplifies the complexity of time-interleaving (TI) and provides gain for attenuating the 8 b SAR non-idealities, when referred to the ADC input, relaxing its specifications and design. To further reduce power, the 2.5 b MDAC front-end is SHA-less, and an over-range calibration loop that allows operation at multi-GHz input is introduced. A calibration technique is also proposed to align the MDAC and SAR references, whose misalignment would otherwise produce integral non-linearity (INL) degradation. The ADC achieves -61.8 dB THD, 57.1 dB SNR for a 500 MHz input, while for a 2.35 GHz input it achieves -54.7 dB THD, 46.8 dB SNR (55.8 dB SNR excluding the integrated PLL contribution). The time-interleaving spur is 70 dBc. The ADC consumes 150 mW and occupies less than 0.5 mm2.

A 2.7 GHz to 7 GHz Fractional-N LC-PLL Utilizing Multi-Metal Layer SoC Technology in 28 nm CMOS

A fractional-N LC-PLL in 28 nm CMOS that uses vertical layout integration techniques to achieve area reduction without performance penalties is proposed. The design utilizes multi-metal layers to vertically integrate dual interposed inductors on top of the active PLL circuit elements, resulting in an area of 0.07 mm2. The PLL covers a wide-frequency range from 2.7 GHz to 7 GHz, consuming a total power of 14 mW. At 7 GHz, the RMS jitter is 0.56 ps in integer mode and 1.1 ps in fractional mode.

A 19 mW/lane Serdes transceiver for SFI-5.1 application

A low-power, small-area transceiver PHY that supports SFI-5.1 is fabricated in standard 40 nm CMOS, supporting rates up to 50 Gb/s. The combined active core area of the receiver (RX) and transmitter (TX) occupies only 0.08 mm2 per lane. The RX can handle 0.65 UI (RJ + DJ) plus 0.49 UI additional sinusoidal input jitter, and the TX has only 5.4 ps of ISI. Sixteen lanes plus deskew and clock source channels consume 19 mW of power at 3.125 Gb/s per lane.

A 0.5–9.5-GHz, 1.2-

A phase-locked loop (PLL) architecture is proposed for improved efficiency of power and thermal management techniques in system-on-chips (SoCs). PLL architecture introduces two techniques: a dual-stage phase-acquisition loop filter that enables fast lock time of 1.2 μs without any frequency overshoots and a nonlinear DCO that enables a wide frequency range of 0.5-9.5 GHz and a low period jitter of ±1.25%UI p-p with a single wideband tuning. With this proposed PLL architecture, SoC can continue its operation without any interruption caused by frequency overshoots during power and thermal management techniques like dynamic core-count scaling and dynamic voltage frequency scaling. The PLL achieves 0.45 ps rms period jitter at 3.25 GHz in fractional-N mode operation, while consuming a total power of 7.1 mW.

\mu \text{s}

A 28 nm CMOS multistandard TV tuner is presented. A power-efficient RF front end and >80 dB dynamic range ΔΣ ADC, together with a smart AGC algorithm, enable this tuner to achieve 64 dB ATSC A/74 N+6 ACI while dissipating only 180 mW. A baseband resistor weighting harmonic rejection mixer clocked by a 7-13.6 GHz PLL and single-edge-triggered shift registers achieves >58 dB harmonic rejection ratio at frequencies up to 827 MHz.

Lock-Time Fractional-N DPLL With ±1.25%UI Period Jitter in 16-nm CMOS for Dynamic Frequency and Core-Count Scaling

Todays multicore processors and complex multimedia SoCs incorporate power management techniques such as dynamic frequency scaling (DFS), which dynamically changes operating frequencies, and dynamic core-count scaling (DCCS), which rapidly power cycles the cores between active and idle states. For digital clocking in such SoCs, the PLL needs to support rapid frequency change and fast locking, both without frequency overshoot, so that SoCs can continue operation without interruption during DFS and start operation right after PLL reset is released during DCCS. Moreover, digital clocking PLLs are also required to have a wide frequency range, low period jitter (JP) and low power. Conventional PLLs like [1] use coarse and fine frequency tuning to achieve both low JP, as well as wide frequency range, but may produce frequency overshoots during initial binary frequency search and during DFS, which can span over multiple coarse bands. Furthermore, a conventional proportional-integral (PI) filter [2] suffers from a tradeoff between fast locking and frequency overshoot. These conventional approaches require the SoC to stop using the PLL clock for thousands of clock cycles to mask these frequency overshoots and cause overhead in DFS and DCCS optimization [6]. Another drawback of conventional PLLs [1-4] is the use of a linearly-tuned DCO (fixed frequency steps), which is not well suited for achieving both wide frequency range and constant JP measured in clock unit-interval percentage (%UI). A constant JP (%UI) is optimal for SoC digital clocking, as a constant percentage of the clock period can be allocated for clock-uncertainties during logic synthesis at any frequency. To address these issues, two techniques are proposed in this DPLL architecture: a) a dual-stage phase-acquisition-based loop filter (DALF), which incorporates a first-order loop for phase-acquisition to achieve fast locking without frequency overshoot, and b) a nonlinear DCO (NDCO), which achieves constant JP across wide frequency range. Using these techniques, a digital PLL in 16nm CMOS achieves ±1.25%UI peak-to-peak JP (p-p JP) over a 0.5-to-9.5GHz range with a short lock-time of 1.2μs.

A 180 mW multistandard TV tuner in 28 nm CMOS

A fractional-N LCPLL in 28nm CMOS that uses vertical layout integration techniques to achieve area reduction is proposed. The design utilizes a multimetal layer interposed inductor pair that is stacked on top of the active PLL circuit elements, resulting in an area of 0.07mm2. The PLL covers a wide-frequency range from 2.7GHz to 7GHz, consuming a total power of 14mW. At 7GHz, the RMS jitter is 0.56ps at integer mode and 1.1ps at fractional mode.