Ichiro Fujimori

A 90-dB SNR 2.5-MHz output-rate ADC using cascaded multibit delta-sigma modulation at 8/spl times/ oversampling ratio

A 16-b 2.5-MHz output-rate analog-to-digital converter (ADC) for wireline communications and high-speed instrumentation has been developed. A 2-1-1 cascaded delta-sigma modulator (DSM) employing 4-b quantizers in every stage makes all quantization noise sources negligible at 8/spl times/ oversampling ratio, Data weighted averaging with bi-directional rotation eliminates tones generated by multibit digital-to-analog converter (DAC) nonlinearity to increase the spurious-free dynamic-range (SFDR). Switched-capacitor design techniques using low-threshold transistors reduce front-end sampling distortion. The 24.8 mm/sup 2/ chip in 0.5-/spl mu/m CMOS also integrates the decimation filter and voltage reference. The ADC achieves 90-dB signal-to-noise ratio (SNR) in the 1.25-MHz bandwidth and 102-dB SFDR with 270-mW power dissipation.

A 1.5 V, 4.1 mW dual channel audio delta-sigma D/A converter

This stereo /spl Delta//spl Sigma/ DAC for portable digital-audio consumes 4.1 mW at 1.5 V supply. The DAC has 90 dB dynamic range over a 20 Hz-20 kHz passband. The 5.3 mm/sup 2/ chip in 0.6 /spl mu/m CMOS includes low-threshold devices.

A multibit delta-sigma audio DAC with 120-dB dynamic range

A 24-bit 192-kHz sample-rate digital-to-analog converter (DAC) achieves 120-dB A-weighted dynamic range in the 20-kHz band, and consumes 310 mW with a 5-V power supply. A third-order five-bit /spl Delta//spl Sigma/ architecture optimized for high-end consumer audio has been developed and used. A switched-capacitor (SC) DAC combined with infinite-impulse response (IIR) and finite-impulse response (FIR) filters is employed to increase immunity to clock jitter, and reduce analog power. Partial-range dynamic element matching (DEM) enhances mismatch shaping with reduced circuit overhead. The 7.8-mm/sup 2/ chip fabricated in 0.5-/spl mu/ m CMOS integrates a stereo DAC and all functions required for DVD-audio playback.

A 5-V single-chip delta-sigma audio A/D converter with 111 dB dynamic range

A 5-V 24-b audio delta-sigma A/D converter has been developed. The single chip integrates stereo delta-sigma modulators, a voltage reference, and a decimation filter. A fourth-order cascaded delta-sigma modulator using a local feedback technique was employed to avoid overload without sacrifice in noise performance. A two-stage decimation filter architecture which reduces digital noise was developed. A new multistage comb filter was used for the first-stage, and a bit-serial finite impulse response (FIR) filter was used for the second stage. The 25.8 mm/sup 2/ chip was fabricated in 0.7-/spl mu/m CMOS with low threshold MOS devices. Measured results show 111 dB dynamic range and 103 dB peak signal-to-(noise plus distortion)S/(N+D).

A 500 mW ADC-Based CMOS AFE With Digital Calibration for 10 Gb/s Serial Links Over KR-Backplane and Multimode Fiber

This paper presents the design of an analog-front-end (AFE) integrated into a DSP-based transceiver for both serial 10 Gbps KR-backplane and long-reach-multimode-fiber (LRM) applications. The receiver consists of a programmable gain amplifier (PGA) and a 6-bit 4-way time-interleaved ADC, which is digitally calibrated to compensate for the offset, gain and phase mismatches between the interleaved channels. With a 5 GHz input signal, the ADC achieves overall SNDR of 29 dB, while the measured SNDR of flash sub-ADC is 31.6 dB. The power efficiency FoM of the complete interleaved ADC is 1.4 pJ per conversion step. The PLL uses a calibrated LC-VCO and the TX features a full-rate 3-tap de-emphasis at the output. Inductively tuned buffers connected in tandem are employed to distribute the 10 GHz clock. Random and deterministic jitter measured at the TX output are 0.38 psrms and 2.65 pspp, respectively. Implemented in 65 nm CMOS technology, the AFE occupies an area of 3 mm2 and consumes 500 mW from a 1 V supply. BER of less than 10-15 is measured over legacy backplanes with 26 dB loss at Nyquist and the measured transceiver optical sensitivity is less than -13 dBm for all four LRM stressors, exceeding both the KR and the LRM specifications.

A fully integrated SONET OC-48 transceiver in standard CMOS

This paper presents the first fully integrated, SONET OC-48 (2.488/2.666 Gb/s) transceiver using a standard CMOS process. Careful design methodology combined with a standard CMOS technology allows performance exceeding SONET requirements with the added benefits of reduced power dissipation, higher integration levels, and simplified manufacturability as compared to other fabrication technologies. This chip, designed using a standard 0.18-/spl mu/m CMOS technology, has a total power dissipation of 500 mW and an rms jitter of 1 ps.

OC-192 transmitter in standard 0.18/spl mu/m CMOS

A fully integrated SONET OC-192 transmitter IC using a standard CMOS process consists of an input data register, FIFO, CMU, and 16:1 multiplexer to give a 10Gb/s serial output. A higher FEC rate, 10.7Gb/s, is supported. This chip, using a 0.18/spl mu/m process, exceeds SONET requirements, dissipating 450mW.

21.7 A 500mW digitally calibrated AFE in 65nm CMOS for 10Gb/s Serial links over backplane and multimode fiber

The demand for bandwidth has fueled the deployment of 10Gb/s traffic over legacy data links such as serial backplanes (10GBase-KR) and multimode fiber (10GBase-MMF) which were originally intended for much lower data rates [1,2]. Under severe channel impairments, a DSP-based transceiver provides robust performance and enables power/area scaling with processes [3–5]. This work describes a 65nm CMOS AFE integrated in a DSP-based PHY for 10Gb/s KR/MMF applications.

A Fully Integrated 10-Gb/s Receiver With Adaptive Optical Dispersion Equalizer in 0.13-

A 10 Gb/s receiver, containing an adaptive equalizer, a clock and data recovery, and a de-multiplexer, is implemented in 0.13-mum CMOS. The chip is intended for long-haul optical fiber links where chromatic and polarization mode dispersions are reach-limiting factors. The equalization is performed by a continuous time filter and a two-tap decision feedback equalizer while automatic threshold and phase adjustments are embedded in the CDR. Use of an analog equalizer with digital adaptation garners total power dissipation of 950 mW. Error-free operation over 200 km of single mode fiber is demonstrated. With 140 km of single mode fiber, optical signal to noise ratio penalty is only 2dB. Differential group delay of 100 ps can also be tolerated

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A fully-integrated transceiver in standard 0.18 /spl mu/m CMOS exceeds all SONET OC-48 requirements. The serial interfaces are 2.488 or 2.667 Gb/s CMC and the parallel ones are 622 or 666 Mb/s LVDS. The output clock rms jitter is 1 ps and total power consumption including all the input/output interfaces is 500 mW.