Greg Yeric

Device and technology implications of the Internet of Things

We live in an interconnected world. Computing power once reserved for server rooms now resides in our pockets. Tablets now outsell PCs. As marked as these changes have been, we are now entering a new era of vastly greater connectivity, where people interact with the world around them in entirely new ways. The Internet of Things is in its infancy, so predictions of precisely what it will become are dangerous, but several things are clear. First, the leaf nodes of the network will share some device and technology properties in terms of cost and computing capability, but also analog and wireless functionality. These nodes will interact with people and with the cloud. The “little data” of these interactions needs to integrate seamlessly with the “big data” of the world around them. The trust, security and service components of these interactions lead to further device and technology requirements. This talk looks at the trends and discusses some likely paths forward.

A 65nm random and systematic yield ramp infrastructure utilizing a specialized addressable array with integrated analysis software

This paper describes a yield learning infrastructure that has been developed and deployed to help rapidly ramp 65nm random and systematic yield. This infrastructure consists of a 4Mb addressable-array test circuit with > 8000 unique test structures along with customized software and automated analysis routines to distill the large datasets generated. Examples of the successful application of this methodology are provided.

Infrastructure for successful BEOL yield ramp, transfer to manufacturing, and DFM characterization at 65 nm and below

The challenges presented by deep-submicron interconnect back-end-of-line (BEOL) integration continue to grow in number, complexity, and required resolution at 90 nm and 65 nm. These challenges are causing industry-wide delays in technology deployment as well as low and often unstable yields. The historically observed improvements in time to successful yield ramp and final manufacturing yield as the industry deploys new technology nodes disappeared at 90 nm. Such improvements have been significant factors in fueling the semiconductor industrys growth. Optimized test structures are necessary to measure and analyze the causes for systematic yield loss. This article introduces a novel test structure for BEOL - an infrastructure IP for process monitoring. It also describes a method for characterizing and measuring yield ramp issues and solutions for improving silicon debug and DFM.

The past present and future of design-technology co-optimization

Design-Technology Co-Optimization (DTCO) has evolved from early Design-for-Manufacture (DFM) needs into a multi-faceted multi-lateral co-optimization below 20nm where multiple patterning and FinFETs add significant complexities. Effective DTCO now involves end product metrics applied to a myriad of design-technology choices. This paper will highlight past and present examples of DTCO in practice for low-power SoC design and examine a future of even more complexity that will drive a continued evolution in DTCO.

Physical design and FinFETs

FinFETs have recently overtaken bulk CMOS transistors as the device of choice for systems-on-chip. This paper provides some background on FinFETs together with their associated manufacturing processes and shows how they influence physical design of standard cells as well as place & route and timing closure for larger blocks.

An embedded process monitor test chip architecture

We present a test chip architecture which embeds a thorough set of process characterization ring oscillators into a synthesized digital circuit, such as a processor core. We discuss the motivation, implementation, and results from sub-40nm technology silicon.

Development and Use of Small Addressable Arrays for Process Window Monitoring in 65nm Manufacturing

In this paper we report on the development and use of two scribe-line compatible addressable array test structures in 65 nm technology for routine process window monitoring. One array was dedicated for front-end of line test structures, while a second consists exclusively of back-end test structures. Fast testing allows large-scale sampling of wafer lots in a manufacturing environment. Customized software is used to automate data analysis and calculate figures of merit that enable process and equipment performance to be tracked by process module. Examples of successful application of these arrays in identifying and addressing systematic yield detractors are provided.

Systematic framework for evaluating standard cell middle-of-line robustness for multiple patterning lithography

Abstract. For robust standard cell design, designers need to improve the intercell compatibility for all combinations of cells and cell placements. Multiple patterning lithography colorability check breaks the locality of traditional rule check, and N-wise checks are strongly needed to verify the colorability for layout interactions across cell boundaries. A systematic framework is proposed to evaluate the library-level robustness over multiple patterning lithography from two perspectives, including complete checks on two-row combinations of cells and long-range interactions. With complete checks on two-row combinations of cells, the vertical and horizontal boundary checks are explored to predict illegal cell combinations. For long-range interactions, random benchmarks are generated by cell shifting and tested to evaluate the placement-level efforts needed to reduce the manufacturing complexity from quadruple patterning lithography to triple patterning lithography for the middle-of-line (MOL) layers. Our framework is tested on the MOL layers but can be easily adapted to other critical layers with multiple patterning lithography constraints.

Circuit design perspectives for Ge FinFET at 10nm and beyond

In this paper we study the circuit design implications of Ge vs. Si PMOS FinFETs at the 10 and 7nm nodes, using TCAD calibrated statistical compact models and the ARM predictive benchmarking flow. The ARM predictive flow incorporates advanced-node-relevant layouts, design rules, parasitic RC extraction and wire-loading. We present the first comprehensive simulation study evaluating Ge pFinFETs in a realistic circuit design context and show that the lack of a stressing mechanism, higher leakage and variability results in sub-optimal performance compared to Si in all circuit benchmark metrics.

A 65-nm Random and Systematic Yield Ramp Infrastructure Utilizing a Specialized Addressable Array With Integrated Analysis Software

This paper describes a yield learning infrastructure that has been developed and deployed to help rapidly ramp 65-nm random and systematic yield. This infrastructure consists of a 4-Mb addressable-array test circuit with >8000 unique test structures along with customized software and automated analysis routines to distill the large datasets generated. Examples of the successful application of this methodology are provided.