Gregory Pitner

MoS2 transistors with 1-nanometer gate lengths

A flatter route to shorter channels High-performance silicon transistors can have gate lengths as short as 5 nm before source-drain tunneling and loss of electrostatic control lead to unacceptable leakage current when the device is off. Desai et al. explored the use of MoS2 as a channel material, given that its electronic properties as thin layers should limit such leakage. A transistor with a 1-nm physical gate was constructed with a MoS2 bilayer channel and a single-walled carbon nanotube gate electrode. Excellent switching characteristics and an on-off state current ratio of ∼106 were observed. Science, this issue p. 99 Molybdenum disulfide transistors with carbon nanotube gate electrodes have channel lengths below the silicon scaling limit. Scaling of silicon (Si) transistors is predicted to fail below 5-nanometer (nm) gate lengths because of severe short channel effects. As an alternative to Si, certain layered semiconductors are attractive for their atomically uniform thickness down to a monolayer, lower dielectric constants, larger band gaps, and heavier carrier effective mass. Here, we demonstrate molybdenum disulfide (MoS2) transistors with a 1-nm physical gate length using a single-walled carbon nanotube as the gate electrode. These ultrashort devices exhibit excellent switching characteristics with near ideal subthreshold swing of ~65 millivolts per decade and an On/Off current ratio of ~106. Simulations show an effective channel length of ~3.9 nm in the Off state and ~1 nm in the On state.

Large‐Area Assembly of Densely Aligned Single‐Walled Carbon Nanotubes Using Solution Shearing and Their Application to Field‐Effect Transistors

Dense alignment of single-walled carbon nanotubes over a large area is demonstrated using a novel solution-shearing technique. A density of 150-200 single-walled carbon nanotubes per micro-meter is achieved with a current density of 10.08 μA μm(-1) at VDS = -1 V. The on-current density is improved by a factor of 45 over that of random-network single-walled carbon nanotubes.

Significant Enhancement of Infrared Photodetector Sensitivity Using a Semiconducting Single‐Walled Carbon Nanotube/C60 Phototransistor

A highly sensitive single-walled carbon nanotube/C60 -based infrared photo-transistor is fabricated with a responsivity of 97.5 A W(-1) and detectivity of 1.17 × 10(9) Jones at 1 kHz under a source/drain bias of -0.5 V. The much improved performance is enabled by this unique device architecture that enables a high photoconductive gain of ≈10(4) with a response time of several milliseconds.

Large-area formation of self-aligned crystalline domains of organic semiconductors on transistor channels using CONNECT

Significance Solution-processed organic electronics are expected to pave the way for low-cost large-area electronics with new and exciting applications. However, realizing solution-processed organic electronics requires densely packed transistors with patterned and precisely registered organic semiconductors (OSCs) within the transistor channel with uniform electrical properties over a large area, a task that remains a significant challenge. To address such a challenge, we have developed an innovative technique that generates self-patterned and self-registered OSC film with low variability in electrical properties over a large area. We have fabricated highest density of transistors with a yield of 99%, along with various logic circuits. This work significantly advances organic electronics field to enable large-scale circuit fabrication in a facile and economical manner. The electronic properties of solution-processable small-molecule organic semiconductors (OSCs) have rapidly improved in recent years, rendering them highly promising for various low-cost large-area electronic applications. However, practical applications of organic electronics require patterned and precisely registered OSC films within the transistor channel region with uniform electrical properties over a large area, a task that remains a significant challenge. Here, we present a technique termed “controlled OSC nucleation and extension for circuits” (CONNECT), which uses differential surface energy and solution shearing to simultaneously generate patterned and precisely registered OSC thin films within the channel region and with aligned crystalline domains, resulting in low device-to-device variability. We have fabricated transistor density as high as 840 dpi, with a yield of 99%. We have successfully built various logic gates and a 2-bit half-adder circuit, demonstrating the practical applicability of our technique for large-scale circuit fabrication.

High-performance carbon nanotube field-effect transistors

We demonstrate carbon nanotube (CNT) field-effect transistors (CNFETs) with the highest current drive (per unit layout width)¹ to-date (>100 μA/μm at 400 nm channel length and 1V V_DS), while simultaneously achieving high I_ON/I_OFF (>5,000). This is the first demonstration of CNFETs with CNT density above 100 CNTs/μm consisting of highly-aligned CNTs and achieving both high current drive and high I_ON/I_OFF. The current drives of the demonstrated CNFETs approach that of similarly-scaled and similarly-biased silicon-based field-effect transistors in production in major semiconductor foundries.

Universal Selective Dispersion of Semiconducting Carbon Nanotubes from Commercial Sources Using a Supramolecular Polymer

Selective extraction of semiconducting carbon nanotubes is a key step in the production of high-performance, solution-processed electronics. Here, we describe the ability of a supramolecular sorting polymer to selectively disperse semiconducting carbon nanotubes from five commercial sources with diameters ranging from 0.7 to 2.2 nm. The sorting purity of the largest-diameter nanotubes (1.4 to 2.2 nm; from Tuball) was confirmed by short channel measurements to be 97.5%. Removing the sorting polymer by acid-induced disassembly increased the transistor mobility by 94 and 24% for medium-diameter and large-diameter carbon nanotubes, respectively. Among the tested single-walled nanotube sources, the highest transistor performance of 61 cm2/V·s and on/off ratio >104 were realized with arc discharge carbon nanotubes with a diameter range from 1.2 to 1.7 nm. The length and quality of nanotubes sorted from different sources is compared using measurements from atomic force microscopy and Raman spectroscopy. The transistor mobility is found to correlate with the G/D ratio extracted from the Raman spectra.

N-type doping of carbon nanotube transistors using yttrium oxide (Y 2 O x )

We present a novel, VLSI compatible technique to fabricate n-type carbon nanotube (CNT) transistors using yttrium oxide as gate dielectric. Wafer-scale, aligned CNT transistors with yttrium oxide (Y₂O_x) dielectrics exhibit n-type behavior with I_on/I_off of 10⁶ and subthreshold slope of 95 mV/dec. Controlled, slow evaporation of yttrium (Y) forms a smooth oxide surface that has excellent wetting to CNTs which consistently gives rise to strong n-type behavior in CNT transistors.