H.-S. Philip Wong

Carbon nanotube computer

The miniaturization of electronic devices has been the principal driving force behind the semiconductor industry, and has brought about major improvements in computational power and energy efficiency. Although advances with silicon-based electronics continue to be made, alternative technologies are being explored. Digital circuits based on transistors fabricated from carbon nanotubes (CNTs) have the potential to outperform silicon by improving the energy–delay product, a metric of energy efficiency, by more than an order of magnitude. Hence, CNTs are an exciting complement to existing semiconductor technologies. Owing to substantial fundamental imperfections inherent in CNTs, however, only very basic circuit blocks have been demonstrated. Here we show how these imperfections can be overcome, and demonstrate the first computer built entirely using CNT-based transistors. The CNT computer runs an operating system that is capable of multitasking: as a demonstration, we perform counting and integer-sorting simultaneously. In addition, we implement 20 different instructions from the commercial MIPS instruction set to demonstrate the generality of our CNT computer. This experimental demonstration is the most complex carbon-based electronic system yet realized. It is a considerable advance because CNTs are prominent among a variety of emerging technologies that are being considered for the next generation of highly energy-efficient electronic systems.

Nanoelectronic Programmable Synapses Based on Phase Change Materials for Brain-Inspired Computing

Brain-inspired computing is an emerging field, which aims to extend the capabilities of information technology beyond digital logic. A compact nanoscale device, emulating biological synapses, is needed as the building block for brain-like computational systems. Here, we report a new nanoscale electronic synapse based on technologically mature phase change materials employed in optical data storage and nonvolatile memory applications. We utilize continuous resistance transitions in phase change materials to mimic the analog nature of biological synapses, enabling the implementation of a synaptic learning rule. We demonstrate different forms of spike-timing-dependent plasticity using the same nanoscale synapse with picojoule level energy consumption.

Conduction mechanism of TiN/HfOx/Pt resistive switching memory: A trap-assisted-tunneling model

The conduction mechanism of metal oxide resistive switching memory is debated in the literature. We measured the I-V characteristics below the switching voltages through TiN/HfOx/Pt memory stack and found the conduction cannot be described by the commonly used Poole-Frenkel model, because the fitted dielectric constant and the trap energy are unreasonable as compared to their known values. Therefore, we provide an alternate viewpoint based on a trap-assisted-tunneling model. Agreement of the bias polarity/temperature/resistance state-dependent conduction behavior was achieved between this model and experimental data. And insights for the multilevel capability due to the control of tunneling distance were obtained.

On the Switching Parameter Variation of Metal-Oxide RRAM—Part I: Physical Modeling and Simulation Methodology

The variation of switching parameters is one of the major challenges to both the scaling and volume production of metal-oxide-based resistive random-access memories (RRAMs). In this two-part paper, the source of such parameter variation is analyzed by a physics-based simulator, which is equipped with the capability to simulate a large number ( ~1000) of cyclic SET-RESET operations. By comparing the simulation results with experimental data, it is found that the random current fluctuation experimentally observed in the RESET processes is caused by the competition between trap generation and recombination, whereas the variation of the high resistance states and the tail bits are directly correlated to the randomness of the trap dynamics. A combined strategy with a bilayer dielectric material and a write-verification technique is proposed to minimize the resistance variation. We describe the simulation methodology and discuss the dc results in Part I. The corroboration of the model and the device optimization strategy will be discussed in Part II.

A Low Energy Oxide-Based Electronic Synaptic Device for Neuromorphic Visual Systems with Tolerance to Device Variation

Neuromorphic computing is an emerging computing paradigm beyond the conventional digital von Neumann computation. An oxide-based resistive switching memory is engineered to emulate synaptic devices. At the device level, the gradual resistance modulation is characterized by hundreds of identical pulses, achieving a low energy consumption of less than 1 pJ per spike. Furthermore, a stochastic compact model is developed to quantify the device switching dynamics and variation. At system level, the performance of an artificial visual system on the image orientation or edge detection with 16 348 oxide-based synaptic devices is simulated, successfully demonstrating a key feature of neuromorphic computing: tolerance to device variation.

Cross-Point Memory Array Without Cell Selectors—Device Characteristics and Data Storage Pattern Dependencies

Cross-point memory architecture offers high device density, yet it suffers from substantial sneak path leakages, which result in large power dissipation and a small sensing margin. The parasitic resistance associated with the interconnects further degrades the output signal and imposes an additional limitation on the maximum allowable array size. In this paper, we study the device requirements of a resistive cross-point memory array under the worst-case write and read operations. We focus on the data pattern dependence of the memory array and compare the effect of the memory cell resistance values and resistance ratio for determining the maximum array size. The number of cells in the array can reach 106 with a signal swing > 50% of the reading voltage when Ron is beyond 3 M and Roff/Ron is greater than 2. A large memory cell resistance value can further reduce the power consumption, obviate the need for a large Roff/Ron ratio, and avoid the inclusion of cell selection devices. The effect of the nonlinearity of the I -V characteristics of the memory cells is also investigated. The nonlinearity calls for a substantial tradeoff between the memory cell resistance values and the resistance ratio, and must be taken into consideration for the device design.

MoS2 transistors with 1-nanometer gate lengths

A flatter route to shorter channels High-performance silicon transistors can have gate lengths as short as 5 nm before source-drain tunneling and loss of electrostatic control lead to unacceptable leakage current when the device is off. Desai et al. explored the use of MoS2 as a channel material, given that its electronic properties as thin layers should limit such leakage. A transistor with a 1-nm physical gate was constructed with a MoS2 bilayer channel and a single-walled carbon nanotube gate electrode. Excellent switching characteristics and an on-off state current ratio of ∼106 were observed. Science, this issue p. 99 Molybdenum disulfide transistors with carbon nanotube gate electrodes have channel lengths below the silicon scaling limit. Scaling of silicon (Si) transistors is predicted to fail below 5-nanometer (nm) gate lengths because of severe short channel effects. As an alternative to Si, certain layered semiconductors are attractive for their atomically uniform thickness down to a monolayer, lower dielectric constants, larger band gaps, and heavier carrier effective mass. Here, we demonstrate molybdenum disulfide (MoS2) transistors with a 1-nm physical gate length using a single-walled carbon nanotube as the gate electrode. These ultrashort devices exhibit excellent switching characteristics with near ideal subthreshold swing of ~65 millivolts per decade and an On/Off current ratio of ~106. Simulations show an effective channel length of ~3.9 nm in the Off state and ~1 nm in the On state.

HfOx-Based Vertical Resistive Switching Random Access Memory Suitable for Bit-Cost-Effective Three-Dimensional Cross-Point Architecture

The three-dimensional (3D) cross-point array architecture is attractive for future ultra-high-density nonvolatile memory application. A bit-cost-effective technology path toward the 3D integration that requires only one critical lithography step or mask for reducing the bit-cost is demonstrated in this work. A double-layer HfOx-based vertical resistive switching random access memory (RRAM) is fabricated and characterized. The HfOx thin film is deposited at the sidewall of the predefined trench by atomic layer deposition, forming a vertical memory structure. Electrode/oxide interface engineering with a TiON interfacial layer results in nonlinear I-V suitable for the selectorless array. The fabricated HfOx vertical RRAM shows excellent performances such as reset current (<50 μA), switching speed (<100 ns), switching endurance (>10(8) cycles), read disturbance immunity (>10(9) cycles), and data retention time (>10(5) s @ 125 °C).

A 1 GHz integrated circuit with carbon nanotube interconnects and silicon transistors.

Due to their excellent electrical properties, metallic carbon nanotubes are promising materials for interconnect wires in future integrated circuits. Simulations have shown that the use of metallic carbon nanotube interconnects could yield more energy efficient and faster integrated circuits. The next step is to build an experimental prototype integrated circuit using carbon nanotube interconnects operating at high speed. Here, we report the fabrication of the first stand-alone integrated circuit combining silicon transistors and individual carbon nanotube interconnect wires on the same chip operating above 1 GHz. In addition to setting a milestone by operating above 1 GHz, this prototype is also a tool to investigate carbon nanotubes on a silicon-based platform at high frequencies, paving the way for future multi-GHz nanoelectronics.

Investigating the switching dynamics and multilevel capability of bipolar metal oxide resistive switching memory

HfOx/AlOx bilayer resistive switching devices were fabricated for the study of the switching dynamics of the metal oxide memory. An exponential voltage-time relationship was experimentally observed as follows: the programming pulse widths need for switching exponentially decreased with the increase in the programming pulse amplitudes. Two following programming schemes were proposed to modulate the high resistance state values: (1) exponentially increase the programming pulse width; (2) linearly increase the programming pulse amplitude. Although both of these schemes were effective to achieve the target resistance, the transient current response measurements suggest the second scheme consumes considerably less energy in the programming. A field-driven oxygen ions migration model was utilized to elucidate the above experimentally observed phenomenon.