Gregory S. Mathews

Method and apparatus for independently stopping and restarting functional units

Transparent system interrupt

System and method for translation buffer accommodating multiple page sizes

Cache memory hierarchy having a large write through first level that allocates for CPU read misses only and a small write back second level that allocates for CPU write misses only

Computer system with interrupts transparent to its operating system and application programs

Multi-processing cache coherency protocol on a local bus

Dual-ported, pipelined, two level cache system

Method and apparatus for advancing load operations

Method and apparatus for reduced latency in hold bus cycles

Central processing unit address pipelining