John H. Crawford

The i486 CPU: executing instructions in one clock cycle

The author discusses the design goals of the i486 development program, which were to ensure binary compatibility with the 386 microprocessor and the 387 math coprocessor, increase performance by two to three times over a 386/387 processor system at the same clock rate, and extend the IBM PC standard architecture of the 386 CPU with features suitable for minicomputers. A cache integrated into the instruction pipeline lets this 386-compatible processor achieve minicomputer performance levels. The design and performance of the on-chip cache and the instruction pipeline are examined in detail.<<ETX>>

Introducing the itanium processors

The press and the technical community have generated much excitement and speculation about the IA-64 instruction set and the Itanium processor. Intel and Hewlett-Packard have rolled out (one instruction at a time) the instruction set. Intel is rolling out (one transistor at a time) the Itanium processor and other platform components. This special issue provides the broad technical community with a comprehensive introduction to the concepts and mechanisms that form the basis of the IA-64 instruction set and the related Itanium processor products.

Engineering a production code generator

This paper describes the structure of a code generator formed by merging the best aspects of three code generation techniques: Graham-Glanville parser-driven code generation [G] [GG] [GR] [HG], the register allocation/spill mechanism from the Portable C Compiler [J], and a code template expander [W]. The Graham-Glanville method was modified to use a standard LALR parser and table builder, and the register allocation method was extended in several significant ways in order to make optimal use of a machine with characterized registers. This code generator is a part of the Pascal-86 compiler developed by Intel Corporation as one of several compilers supporting its iAPX-86 (8086) microprocessor family. The language supported by the compiler is an extension of the Draft International Standard Pascal, level 0. Object code generated by this method compares favorably to code produced by other compilers for the 8086, as well as Pascal compilers for other machines. Since its release in March 1981, the code generator has proved to be quite reliable and easy to maintain.

The execution pipeline of the Intel i486 CPU

The integer instruction execution pipeline of the Intel i486 processor is described. The performance of the i486 CPU in a system is related to several systems based on competitive reduced-instruction-set-computer (RISC) processors. The instruction pipeline was designed to execute instructions at a sustained rate of 1 clock per instruction. A key to achieving this rate was the integration of the cache into the pipeline. Another key was pipelining the instruction decoder into two stages to provide a sustained throughput of 1 instruction per clock, while decoding the complex instruction formats of the Intel 386 family architecture. An overview of the pipeline is provided by giving a brief description of each pipeline stage. Then several multiple instruction examples are given to illustrate some key properties of the pipeline.<<ETX>>

Performance Characterization of Decimal Arithmetic in Commercial Java Workloads

Binary floating-point numbers with finite precision cannot represent all decimal numbers with complete accuracy. This can often lead to errors while performing calculations involving floating point numbers. For this reason many commercial applications use special decimal representations for performing these calculations, but their use carries performance costs such as bi-directional conversion. The purpose of this study was to understand the total application performance impact of using these decimal representations in commercial workloads, and provide a foundation of data to justify pursuing optimized hardware support for decimal math. In Java, a popular development environment for commercial applications, the BigDecimal class is used for performing accurate decimal computations. BigDecimal provides operations for arithmetic, scale manipulation, rounding, comparison, hashing, and format conversion. We studied the impact of BigDecimal usage on the performance of server-side Java applications by analyzing its usage on two standard enterprise benchmarks, SPECjbb2005 and SPECjAppServer2004 as well as a real-life mission-critical financial workload, Morgan Stanleys Trade Completion. In this paper, we present detailed performance characteristics and we conclude that, relative to total application performance, the overhead of using software decimal implementations is low, and at least from the point of view of these workloads, there is insufficient performance justification to pursue hardware solutions

A new approach to code motion and its application to hoisting

An approach to code motion and hoisting, a program optimization technique, is discussed. The safety and profitability of optimization in general and hoisting in particular are analyzed. By restricting the analysis to a spanning tree imposed on the program graph, a linear algorithm is developed that provides sufficient but not necessary conditions for hoisting.