Gregory Uehara

A 200 MHz 9-tap analog equalizer for magnetic disk read channels in 0.6 /spl mu/m CMOS

This paper describes an analog discrete-time equalizer that uses switched-capacitor (SC) filtering capable of achieving speeds higher than can otherwise be attained using conventional opamp techniques. The approach employs parallelism and exclusive use of open-loop circuitry in the signal path. Conventional SC filters require technologies with high-quality capacitors to create accurate ratios. The approach eliminates high-quality capacitors in the signal path and is amenable to digital CMOS processes.

An LTE transmitter using a class-A/B power mixer

For an LTE transceiver it is quite challenging to reduce power and area while preserving performance. For large emitted signals the TX dominates power consumption but in the past this situation was sufficiently infrequent not to affect energy consumption. In recent times the statistical distribution of the TX power has shifted upward due to the use of data-intensive communications and the introduction of multi-gain power amplifiers. Therefore to extend battery life in fourth generation terminals, TX consumption at high power (>-10dBm) should be reduced. A second challenge of an FDD LTE TX is noise and distortion emission in the RX band since the TX-to-RX distance, relative to the channel bandwidth, can be much smaller than in previous standards [1].

A 100 MHz A/D interface for PRML magnetic disk read channels

An analog-to-digital interface IC suitable for PRML read channels with a 100 MHz output rate has been designed and fabricated in a 1.2 /spl mu/m CMOS technology. The prototype IC contains a low-pass filter, symbol-rate equalizer, analog-to-digital converter, and generates all required clocks from a single external reference clock. The filters are implemented using a switched-capacitor parallel filter architecture used to implement a 3:1 decimation filter and a 3-tap programmable equalizer. >

Parallelism in analog and digital PRML magnetic disk read channel equalizers

Analog pre-equalization can play an important role in the performance and monolithic implementation of high speed PRML read channels employing detection in the digital domain by reducing the number of quantization levels required in the analog-to-digital converter. The use of the 3-tap raised cosine equalizer as an analog pre-equalizer in a read channel employing digital adaptive equalization is examined. Following this, a parallel filter architecture suitable for implementation of high speed finite-impulse response filters (including the cosine equalizer) in both the analog and digital domain is described. This parallel filter architecture has been used in the analog domain in both a decimation filter and cosine equalizer in a prototype analog-to-digital interface and in the digital domain in a prototype digital adaptive equalizer/Viterbi sequence detector. Both circuits were fabricated in conservative 1.2 /spl mu/m CMOS technologies and operate with output sampling rates of 100 MHz. >

A 755 Mb/s Viterbi decoder for the RM (64, 35, 8) subcode

As speed demands in broadband communication systems increase into the Gb/s region, economical implementation of robust high-speed soft-decision error-correcting decoders becomes necessary. Convolutional codes are one approach that have been widely employed in communication and storage systems. Decoders for convolutional codes have trellis structures and are typically decoded using the Viterbi algorithm. The speed of these decoders is limited by the well-known add-compare-select (ACS) bottleneck. In addition, previously reported decoder implementations use a radix-4 ACS block which processes two symbols per clock cycle. An alternative to convolutional codes are block codes which also have trellis structures that can be decoded using the Viterbi algorithm. Since trellises for block codes have well-defined source and destination states, bi-directional decoding which overcomes the ACS bottleneck states can be employed. Furthermore, processing eight or more symbols per clock cycle becomes practical allowing manageable system clock frequencies in high rate decoders. This paper describes a Viterbi decoder IC for the Reed-Muller (RM) (64,35,8) subcode.