Grzegorz Mrugalski

Embedded deterministic test for low cost manufacturing test

This paper introduces embedded deterministic test (EDT) technology, which reduces manufacturing test cost by providing one to two orders of magnitude reduction in scan test data volume and scan test time. The EDT architecture, the compression algorithm, design flow, experimental results, and silicon implementation are presented.

Low Power Embedded Deterministic Test

This paper presents a novel low power test scheme integrated with the embedded deterministic test environment. It reduces switching rates in scan chains with no hardware modification. Experimental results obtained for industrial circuits indicate that switching activity can be reduced up to 23 times.

X-Press: Two-Stage X-Tolerant Compactor With Programmable Selector

This paper presents X-Press - a new two-stage test-response compactor that can be easily integrated with a multiple scan-chain environment. This compactor preserves all benefits of spatial compaction and offers, due to its overdrive sequential section, compression much higher than the ratio of scan chains to compactor outputs. X-Press is also capable of handling a wide range of unknown (X) state profiles by deploying a two-level scan-chain-selection mechanism. In addition to a new compactor architecture, original contributions of this paper include a detailed analysis of two-level error masking caused by X states and a new algorithm to both rank scan chains and then to determine, in per-pattern mode, scan-chain-selection rules used to suppress X states. Experimental results obtained for a variety of designs show feasibility and efficiency of the proposed compaction scheme, altogether with actual impact of X states on a test-pattern count. Finally, diagnostic capabilities of the proposed scheme accompanied by further experimental results are also analyzed.

Cellular automata-based test pattern generators with phase shifters

The paper presents a novel, comprehensive and systematic methodology, which can be used to automate synthesis of cellular automata-based test pattern generators with phase shifters. First, a very fast and simple simulation framework is proposed to either verify or generate maximum-length linear finite state machines such as cellular automata or linear feedback shift registers. Subsequently, a new framework is presented for efficient selection of phase shifters that satisfy criteria of channel separation and circuit complexity. As shown in the paper, it is possible to synthesize, in a time-efficient manner, very large cellular automata and their corresponding fast phase shifters for built-in self-test applications with guaranteed structural and functional properties.

Low-Power Test Data Application in EDT Environment Through Decompressor Freeze

This paper presents a new low-power test scheme integrated with the embedded deterministic test environment. The key contribution of this paper is a flexible test cube encoding scheme, which, in conjunction with a continuous flow decompressor, allows one to significantly reduce toggling rates when test patterns are fed into scan chains. The proposed solution requires neither additional design for testability logic nor modifications to the circuit under test. Experimental results obtained for industrial designs indicate that using this nonintrusive technique reduces switching activity to such extent that the resultant scan-in power consumption is similar to that of the functional mode, thus alleviating problems that are related to average and peak power dissipation, overheating, and risk of reliability degradation. Our approach seamlessly integrates with test logic synthesis flow, and it does not compromise compression ratios. Moreover, it fits well into various design paradigms, including modular design flow where modules come with individual decompressors and compactors.

Comparative study of CA-based PRPGs and LFSRs with phase shifters

The paper presents a comparative study of randomness properties of patterns generated by one-dimensional linear hybrid cellular automata (LHCA) and linear feedback shift registers (LFSRs) with phase shifters on their outputs. It is shown that properly synthesized phase shifters allow LFSRs to match performance of the LHCAs as pseudo-random pattern generators (PRPGs), in marked contrast to several suggestions that LHCAs can outperform LFSRs in variety of testing applications.

Synthesis of pattern generators based on cellular automata with phase shifters

The paper presents novel algorithms for the automated synthesis of cellular automata-based test generators with phase shifters. As shown in the paper, it is possible to synthesize in time-efficient manner very large cellular automata and their corresponding fast phase shifters for BIST applications with guaranteed structural and functional properties.

Linear independence as evaluation criterion for two-dimensional test pattern generators

The probability of obtaining desired test patterns in subsequences generated by two-dimensional test pattern generators is examined. Various architectures of generators comprising of linear feedback shift registers, cellular automata and associated phase shifters are thoroughly investigated. Two new algorithms that can be employed to synthesize phase shifters minimizing linear dependencies and assuring highly balanced usage of all generator stages are also introduced.

High speed ring generators and compactors of test data [logic IC test]

This paper presents a new highly modular architecture of generators and compactors of test patterns. This structure has fewer levels of logic, smaller fan-out, reduced area, and operates at faster speed than external feedback LFSRs, internal feedback LFSRs, and cellular automata, all implementing the same characteristic polynomial.

2D test sequence generators

In experiments examining test pattern generators using LFSRs with and without phase shifters as sources of 2D stimuli, generators with phase shifters consistently achieved higher hit ratios than those without. Moreover, a new algorithm synthesizes phase shifters, minimizes linear dependencies, and balances the use of generator stages.