Guanbin Xing

Frequency offset and I/Q imbalance compensation for direct-conversion receivers

Two types of wireless system imperfections, namely, frequency offset and in-phase/quadrature (I/Q) imbalance, are addressed in this paper. The I/Q imbalance in radio frequency (RF) direct-conversion not only introduces an unwanted in-band image interference but also degrades the accuracy of carrier estimation. Toward this end, we propose a pilot-based scheme for both frequency offset and I/Q imbalance compensation at the baseband. A low-cost nonlinear least squares (NLS) frequency estimator robust to the I/Q imbalance is developed. Also derived is an I/Q imbalance compensation structure that consists of two stages: a finite impulse response (FIR) filter that compensates the frequency dependent imbalance; and an asymmetric phase compensator that corrects the frequency independent error. The compensation coefficients are optimized by exploiting the phase rotation embedded in the pilot symbols. Both computer simulations and experiment results verify the effectiveness of the proposed scheme in various I/Q imbalance scenarios.

Frequency offset and I/Q imbalance compensation for OFDM direct-conversion receivers

Two types of RF front-end imperfections in direct-conversion receivers, namely frequency offset and I/Q imbalance, are addressed. The I/Q imbalance not only introduces an unwanted image interference, but also degrades the accuracy of carrier estimation. We propose a pilot-based scheme for both frequency offset and I/Q imbalance compensation. A nonlinear least squares (NLS) frequency estimator, robust to the I/Q imbalance, is developed. Also derived is an I/Q compensation structure that consists of two stages: the frequency dependent imbalance is compensated with an FIR filter whereas the frequency independent part is corrected with an asymmetric phase compensator. The compensation coefficients are optimized by restoring the phase rotation embedded in the pilot symbols.

Implementing an OFDM Receiver on the RaPiD Reconfigurable Architecture

Field-programmable gate arrays (FPGAs) have become an extremely popular implementation technology for custom hardware because they offer a combination of low cost and very fast turnaround. Because of their in-system reconfigurability, FPGAs have also been suggested as an efficient replacement for application-specific integrated circuits (ASICs) and digital signal processors (DSPs) for applications that require a combination of high performance, low cost, and flexibility. Unfortunately, the use of FPGAs in mobile embedded systems platforms is hampered by the very large overhead of FPGA-based architectures. Coarse-grained configurable architectures can reduce this overhead substantially by taking advantage of the application domain to specialize the reconfigurable architecture via coarse-grained components and interconnects. This paper presents the design and implementation of an OFDM receiver in the RaPiD reconfigurable architecture as a case study for comparing the relative cost and performance of ASIC, DSP, FPGA, and coarse-grained reconfigurable architectures. RaPiD is a coarse-grained reconfigurable architecture specialized to the domain of signal and image processing. The RaPiD architecture provides a reconfigurable pipelined datapath controlled by efficient reconfigurable control logic: We have implemented the computationally intensive parts of an OFDM receiver on the RaPiD architecture and have developed careful estimates of corresponding implementations in representative ASIC, DSP and FPGA technology. Our results show that, for this application, RaPiD fills the cost/performance gap between programmable DSP and ASIC architectures, achieving a factor of 6 better than a DSP implementation but a factor of 6 less than an ASIC implementation.

An Emulator for Exploring RaPiD Configurable Computing Architectures

The RaPiD project at the University of Washington has been studying configurable computing architectures optimized for coarse-grained data and computation units and deep computation pipelines. This research targets applications in the signal and image-processing domain since they make the greatest demand for computation and power in embedded and mobile computing applications, and these demands are increasing faster than Moores law. This paper describes the RaPiD Emulator, a system that will allow the exploration of alternative configurable architectures in the context of benchmark applications running in real-time. The RaPiD emulator provides enough FPGA gates to implement large RaPiD arrays, along with a high-performance streaming memory architecture and high-bandwidth data interfaces to a host processor and external devices. Running at 50 MHz, the emulator is able to achieve over 1 GMACs/second.

An LDPC-based terrestrial multimedia broadcasting (TMB) system: design, implementation and experimental results

The paper describes a multicarrier terrestrial multimedia broadcasting (TMB) system that offers system performance and service versatility suitable for future digital broadcasting networks. The new system utilizes variable rate, variable size LDPC (low-density parity-check) codes to allow simultaneous transmission of different programs with diverse requirements. A prototype system is implemented based on the proposed protocol. Results from both lab tests and field trials demonstrate significant performance advantages of the new design over existing systems such as DVB-T.