Guang-Hwa Shiue

Noise reduction using compensation capacitance for bend discontinuities of differential transmission lines

Differential signaling has become a popular choice for multigigabit digital applications in favor of its low-noise generation and high common-mode noise immunity. Recalling from the full-wave solution of S-parameters, this paper presented a design methodology of analysis scheme to extract the equivalent circuits of discontinuities observed on the strongly coupled differential lines. Signal integrity effects of the bent differential transmission lines in a high-speed digital circuit were then simulated in the time domain. A dual back-to-back routing topology of bent differential lines to reduce the common-mode noise was further investigated. To alleviate the common-mode noise at the receiver, a novel compensation scheme in use of the shunt capacitance was also proposed. Furthermore, the comparison between the simulation and measured results validated the equivalent circuit model, coupled bends with compensation capacitance patch, and analysis approach

Delaunay–Voronoi Modeling of Power-Ground Planes With Source Port Correction

An efficient Delaunay-Voronoi modeling of the power-ground planes suitable directly for SPICE compatibity is proposed to deal with the ground bounce noise and decoupling capacitors placement problems for the high-speed digital system designs. The model consists of virtual ports and triangular meshes with the lumped circuit elements, in which all the element values can be related to the mesh geometry shape by the analogy between the circuit equations and Maxwells equations. Since the analogy fails to apply due to the singular fields near the input/output pins, the via effect of driving and sensing ports is not negligible and an analytical expression from the Hankel function is thus presented for the correction term. A simple rule has been investigated for the model with minimum lumped circuit elements to accurately represent the power-ground planes over the frequency range of interests. The full-wave simulation and measurement results verify the good correlations with the proposed models for the impedance responses of regular and defective plane shapes.

A Systematic Design to Suppress Wideband Ground Bounce Noise in High-Speed Circuits by Electromagnetic-Bandgap-Enhanced Split Powers

In this paper, the split power planes with electromagnetic bandgap structures enhancement is proposed for the wideband suppression of ground bounce noise in high-speed printed circuit boards. A systematic design procedure is presented, featuring a modified analytic design formula, a novel compact electromagnetic bandgap layout, and a discussion on the minimum number of cascaded rows. As it is capable of selectively suppressing the ground bounce noise at several desired frequencies, the approach is applied to deal with the coupled noise between two isolation islands and the ground bounce noise induced by signal line crossing the split power planes. Successful noise suppression over an ultrawide band from dc to 5 GHz and reduction of the peak ground bounce noise in the time domain by 75% by an electromagnetic bandgap strip 1.44 cm wide is demonstrated. Good agreement is seen from the comparison between simulation and experimental results

Comparisons between serpentine and flat spiral delay lines on transient reflection/transmission waveforms and eye diagrams

In contrast to the commonly employed single-ended delay lines, the employment of differential signaling may alleviate the occurrence of crosstalk and improve the signal integrity. This paper qualitatively investigates the time-domain reflection (TDR) and time-domain transmission (TDT) waveforms for the single-ended and differential delay lines with the serpentine and flat spiral routing schemes. A numerical formula is then proposed to quantitatively predict the voltage levels of the saturated near-end and far-end propagating crosstalk noises among the sections of differential delay lines. Signal waveforms and eye diagrams of the four basic routing schemes are obtained by HSPICE simulations, demonstrating that the combination of differential signaling and flat spiral layouts can exhibit the best delay-line performance. Furthermore, both the TDR and TDT measurements for differential delay lines are performed to validate the exactitude of proposed analyses.

Analysis of Common-Mode Noise for Weakly Coupled Differential Serpentine Delay Microstrip Line in High-Speed Digital Circuits

This study investigates the mechanisms of generation of the transient transmission common-mode noise in a differential serpentine delay line under weak coupling condition. The generation mechanism and the frequency of common-mode noise are investigated with reference to the time-domain transmission waveform and the differential-to-common mode conversion mixed-mode S-parameters using the circuit solver HSPICE and 3-D full-wave simulator HFSS, respectively. The generation mechanisms of common-mode noise include length mismatch between vertical-turn-coupled traces, the length effect of parallel-coupled traces, and the crosstalk noise effect. Moreover, a graphical method based on wave tracing is presented to illustrate the cancellation mechanism of near-end common-mode noise for the symmetrical differential serpentine delay line. Some practical, commonly used layout routings of the differential serpentine delay line are investigated. Some important design guidelines are provided to help design differential serpentine delay line with low common-mode noise. A comparison between simulated and measured results validates the equivalent circuit model and analytical approach.

Reduction in Reflections and Ground Bounce for Signal Line Over Slotted Power Plane Using Differential Coupled Microstrip Lines

This paper investigates the noise reduction in the slot-induced ground bounce noise by using differential signaling. An efficient 2-D finite-difference time-domain method together with equivalent circuits for both the differential line and the slot is established and simulations are performed for a three-layer structure to characterize the ground bounce coupling. A simple model is then proposed to understand how the differential coupled microstrip lines can help reduce ground bounce. Different factors which affect noise reduction are investigated, such as the coupling coefficient, rising time, skew of differential signaling, and structure asymmetry in slotline. An experimental setup is devised to demonstrate the noise coupling between signal lines due to the slot-induced ground bounce and significant noise reduction by employing differential signaling. A favorable comparison between the simulation and measured results validates the proposed equivalent circuit model and analysis approach.

Composite effects of reflections and ground bounce for signal line through a split power plane

The signal propagating along a microstrip line over a slot on the power plane will suffer from composite effects of reflected noise by a discontinuity in signal return path and ground bounce between power and ground planes. A new equivalent circuit model is proposed and simulations are performed for multilayer structures to characterize these composite effects. An experimental setup is devised to demonstrate significant coupling between signal lines due to the slot-induced ground bounce. Favorable comparison between the simulation and measured results validates the proposed equivalent circuit model and analysis approach.

Reflection Enhanced Compensation of Lossy Traces for Best Eye-Diagram Improvement Using High-Impedance Mismatch

As the signal rates increase toward the multigigabit range, the lossy effect of typical transmission lines on the signal quality of printed circuit boards has become a more and more significant issue. This paper introduces the concept of reflection gain resulted from the high-impedance mismatch to improve the eye diagram at the receiving end by inserting the inductance or high-impedance line between the signal trace and matched termination. A systematic design methodology is also proposed here to tell how to resolve the optimal high-impedance elements for the finest compensation efficiency. Moreover, with the optimal inductance, a design formula based on the circuit theory is derived accordingly to estimate the approximate length of high-impedance line and after that, the ultimate performance of this compensation method is also evaluated. Eventually, some experiments are imple mented to validate the design technique.

Fewest vias design for microstrip guard trace by using overlying dielectric

The unwanted ringing noise owing to the resonance related to the spacing of shorting vias on microstrip guard traces might degrade the signal quality of adjacent interconnects. This paper proposes a novel design method to reduce the ringing noise by overlying a thin dielectric with higher dielectric constant onto the original microstrip substrate. It has the advantages of minimizing the required number of shorting vias and achieving less restricted circuit routing.

An Integrated Signal and Power Integrity Analysis for Signal Traces Through the Parallel Planes Using Hybrid Finite-Element and Finite-Difference Time-Domain Techniques

This paper presents a numerical approach that combines the finite-element time-domain (FETD) method and the finite-difference time-domain (FDTD) method to model and analyze the two-dimensional electromagnetic problem concerned in the simultaneous switching noise (SSN) induced by adjacent signal traces through the coupled-via parallel-plate structures. Applying FETD for the region having the source excitation inside and FDTD for the remaining regions preserves the advantages of both FETD flexibility and FDTD efficiency. By further including the transmission-line simulation, the signal integrity and power integrity issues can be resolved at the same time. Furthermore, the numerical results demonstrate which kind of signal allocation between the planes can achieve the best noise cancellation. Finally, a comparison with the measurement data validates the proposed hybrid techniques.