Wei-Da Guo

Noise reduction using compensation capacitance for bend discontinuities of differential transmission lines

Differential signaling has become a popular choice for multigigabit digital applications in favor of its low-noise generation and high common-mode noise immunity. Recalling from the full-wave solution of S-parameters, this paper presented a design methodology of analysis scheme to extract the equivalent circuits of discontinuities observed on the strongly coupled differential lines. Signal integrity effects of the bent differential transmission lines in a high-speed digital circuit were then simulated in the time domain. A dual back-to-back routing topology of bent differential lines to reduce the common-mode noise was further investigated. To alleviate the common-mode noise at the receiver, a novel compensation scheme in use of the shunt capacitance was also proposed. Furthermore, the comparison between the simulation and measured results validated the equivalent circuit model, coupled bends with compensation capacitance patch, and analysis approach

Delaunay–Voronoi Modeling of Power-Ground Planes With Source Port Correction

An efficient Delaunay-Voronoi modeling of the power-ground planes suitable directly for SPICE compatibity is proposed to deal with the ground bounce noise and decoupling capacitors placement problems for the high-speed digital system designs. The model consists of virtual ports and triangular meshes with the lumped circuit elements, in which all the element values can be related to the mesh geometry shape by the analogy between the circuit equations and Maxwells equations. Since the analogy fails to apply due to the singular fields near the input/output pins, the via effect of driving and sensing ports is not negligible and an analytical expression from the Hankel function is thus presented for the correction term. A simple rule has been investigated for the model with minimum lumped circuit elements to accurately represent the power-ground planes over the frequency range of interests. The full-wave simulation and measurement results verify the good correlations with the proposed models for the impedance responses of regular and defective plane shapes.

A Systematic Design to Suppress Wideband Ground Bounce Noise in High-Speed Circuits by Electromagnetic-Bandgap-Enhanced Split Powers

In this paper, the split power planes with electromagnetic bandgap structures enhancement is proposed for the wideband suppression of ground bounce noise in high-speed printed circuit boards. A systematic design procedure is presented, featuring a modified analytic design formula, a novel compact electromagnetic bandgap layout, and a discussion on the minimum number of cascaded rows. As it is capable of selectively suppressing the ground bounce noise at several desired frequencies, the approach is applied to deal with the coupled noise between two isolation islands and the ground bounce noise induced by signal line crossing the split power planes. Successful noise suppression over an ultrawide band from dc to 5 GHz and reduction of the peak ground bounce noise in the time domain by 75% by an electromagnetic bandgap strip 1.44 cm wide is demonstrated. Good agreement is seen from the comparison between simulation and experimental results

Fast Methodology for Determining Eye Diagram Characteristics of Lossy Transmission Lines

As the speed of signal through an interconnection increases toward the multigigabit ranges, the effects of lossy transmission lines on the signal quality of printed circuit boards becomes a critical issue. To evaluate the eye diagram and thus the signal integrity in the modern digital systems, this paper proposes a fast methodology that employs only two anti-polarity one-bit data patterns instead of the pseudo-random bit sequence as input sources to simulate the worst-case eye diagram. Analytic expressions are derived for the impulse response of the lossy transmission lines due to the skin-effect loss, while the Kramers-Kronig relations are employed to deal with the noncausal problem related to the dielectric loss. Two design graphs that can be used to rapidly predict the eye diagram characteristics versus the conductive and dielectric losses are then constructed and based on which, the maximally usable length of transmission lines under a certain signal specification can be easily acquired. At last, the time-domain simulations and experiments are implemented to verify the exactitude of proposed concept.

Comparisons between serpentine and flat spiral delay lines on transient reflection/transmission waveforms and eye diagrams

In contrast to the commonly employed single-ended delay lines, the employment of differential signaling may alleviate the occurrence of crosstalk and improve the signal integrity. This paper qualitatively investigates the time-domain reflection (TDR) and time-domain transmission (TDT) waveforms for the single-ended and differential delay lines with the serpentine and flat spiral routing schemes. A numerical formula is then proposed to quantitatively predict the voltage levels of the saturated near-end and far-end propagating crosstalk noises among the sections of differential delay lines. Signal waveforms and eye diagrams of the four basic routing schemes are obtained by HSPICE simulations, demonstrating that the combination of differential signaling and flat spiral layouts can exhibit the best delay-line performance. Furthermore, both the TDR and TDT measurements for differential delay lines are performed to validate the exactitude of proposed analyses.

Reflection Enhanced Compensation of Lossy Traces for Best Eye-Diagram Improvement Using High-Impedance Mismatch

As the signal rates increase toward the multigigabit range, the lossy effect of typical transmission lines on the signal quality of printed circuit boards has become a more and more significant issue. This paper introduces the concept of reflection gain resulted from the high-impedance mismatch to improve the eye diagram at the receiving end by inserting the inductance or high-impedance line between the signal trace and matched termination. A systematic design methodology is also proposed here to tell how to resolve the optimal high-impedance elements for the finest compensation efficiency. Moreover, with the optimal inductance, a design formula based on the circuit theory is derived accordingly to estimate the approximate length of high-impedance line and after that, the ultimate performance of this compensation method is also evaluated. Eventually, some experiments are imple mented to validate the design technique.

Signal/Power Integrity Modeling of High-Speed Memory Modules Using Chip-Package-Board Coanalysis

Under the platform of a high-speed double-data-rate three (DDR3) memory module, a modeling method considering all the significant effects from the chip, package, and board levels is developed to identify and investigate the critical nets affecting the signal or power integrity (SI/PI). For SI part, accurate modeling strategies for signal channels are verified by experiments on samples of address lines. The following what-if analyses of eye diagrams help to identify the discontinuities of package trace to be the bottlenecks and have great effects on the eye diagrams. For PI issues, the modeling methodologies for power distribution networks of data buses are demonstrated and validated with the results of measurement. The analysis indicates that the parasitic effects of the low-cost package structure are the most critical, depicting the importance of improved package design in the next-generation DDR memory modules.

Fewest vias design for microstrip guard trace by using overlying dielectric

The unwanted ringing noise owing to the resonance related to the spacing of shorting vias on microstrip guard traces might degrade the signal quality of adjacent interconnects. This paper proposes a novel design method to reduce the ringing noise by overlying a thin dielectric with higher dielectric constant onto the original microstrip substrate. It has the advantages of minimizing the required number of shorting vias and achieving less restricted circuit routing.

An Integrated Signal and Power Integrity Analysis for Signal Traces Through the Parallel Planes Using Hybrid Finite-Element and Finite-Difference Time-Domain Techniques

This paper presents a numerical approach that combines the finite-element time-domain (FETD) method and the finite-difference time-domain (FDTD) method to model and analyze the two-dimensional electromagnetic problem concerned in the simultaneous switching noise (SSN) induced by adjacent signal traces through the coupled-via parallel-plate structures. Applying FETD for the region having the source excitation inside and FDTD for the remaining regions preserves the advantages of both FETD flexibility and FDTD efficiency. By further including the transmission-line simulation, the signal integrity and power integrity issues can be resolved at the same time. Furthermore, the numerical results demonstrate which kind of signal allocation between the planes can achieve the best noise cancellation. Finally, a comparison with the measurement data validates the proposed hybrid techniques.

Enhanced Microstrip Guard Trace for Ringing Noise Suppression Using a Dielectric Superstrate

Grounded guard traces are increasingly used to reduce the coupling-induced crosstalk, but the incurred ringing noise will strongly limit the performance for the microstrip structures. This paper describes the generation mechanism of the ringing noise and derives an analytical formula of the noise magnitude. Besides, an enhanced microstrip guard trace design is proposed to eliminate the ringing noise by covering the original microstrip structure with a superstrate of higher permittivity. A design space versus the superstrate thickness and the dielectric constant are constructed and in which, the guard trace needs be grounded at the two ends only without causing any ringing noise. Finally, the time-domain simulations and experiments are performed to verify the proposed concept.