Guangjun Xie

Modular design of QCA carry flow adders and multiplier with reduced wire crossing and number of logic gates

Summary Quantum-dot cellular automata (QCA) is an emerging technology with the rapid development of low-power high-performance digital circuits. In order to reduce the wire crossings and the number of logic gates in QCA circuits, this paper proposes a full adder named Tile full adder based on a 3 × 3 grid module, a Tile bit-serial adder based on the new full adder and a Diverse Clock Tile bit serial adder (DC Tile bit-serial) adder based on the new full adder and a DC multiplier network. Based on previously mentioned circuit units an improved carry flow adder (CFA) named Tile CFA and two types of carry delay multiplier (CDM) named Tile CDM and DC Tile CDM (DC Tile CDM) with different sizes are presented. All of the proposed QCA circuits are designed and simulated with QCADesigner. Simulation results show that these circuit designs not only implement the logic functions correctly but also achieve a significant performance improvement. Copyright

An All-Digital PLL for Video Pixel Clock Regeneration Applications

This paper presents an all-digital PLL (ADPLL) for the pixel clock regeneration in analog video signal digitization applications. A fine frequency resolution, 1-1-1 MASH structure based fractional-N PLL (FN-PLL) is used as the Digital-Controlled Oscillator (DCO). Two loop filters which are triggered by different clock frequencies and both with adaptive gain controllers are combined together working at different states to increase both the tracking speed and the locked jitter performance. The ADPLL maximum output frequency is determined by the FN-PLL’s voltage-controlled oscillator (VCO) which can be upper than 1Ghz. It covers any VESA and HDTV specification requirements even at 4X over-sampling ratio. A test chip contains this ADPLL prototype has been implemented in a 0.13um CMOS technology. The layout area is about 0.2mm2, the measured RMS jitter is 32.4ps.

The Fundamental Primitives with Fault-Tolerance in Quantum-Dot Cellular Automata

Since conventional CMOS technology has met its development bottleneck, an alternative technology, quantum-dot cellular automata (QCA), attracted researchers’ attention and was studied extensively. The manufacturing process of QCA, however, is immature for commercial production because of the high defect rate. Seeking for designs that display excellent performance shows significant potentials for practical realizations. In the paper we propose a 5 × 5 module, which not only can implement three-input majority gate but also can realize five-input majority gate by adding another two inputs. A comprehensive analysis is made in terms of area, number of cells, energy dissipation and fault tolerance against single-cell omission defects. In order to testify the superiority of the proposed designs, preexisting related designs are tested and compared. Weighing up above four kinds of factors and technical feasibility, proposed majority gates perform fairly well. Further, we take full adders and multi-bit adders as illustrations to display the practical application of proposed majority gates. The detailed comparisons with previous adders reveal that proposed 5 × 5 module behaves well in circuits, especially the high degree of fault tolerance and the relatively small area, complexity and QCA cost, thereby making it more suitable for practical realizations in large circuit designs.

A novel design and analysis of comparator with XNOR gate for QCA

Abstract Quantum-dot cellular automata (QCA) is an emerging nanotechnology. It has attracted much interest for its potential for faster speed, smaller size, and lower power dissipation than conventional transistor-based technology. QCA XNOR gate is proposed in this letter and the reliability, AVG Energy Dissipation of Circuit (AVG EDC) of it have been analyzed. Multi-bit comparators have been implemented with preferable XNOR gate proposed in this letter and they have lower complexity and Efficient Complexity than previous ones. The detailed simulation results using QCADesigner are presented finally.

An Output-Capacitorless Ultra-Low Power Low-Dropout Regulator

This paper proposes an output-capacitorless low-dropout (LDO) regulator with ultra-low quiescent power. It applies an adaptive error amplifier to improve the bandwidth and transient response during...

A Hebbian-Based Quantum Learning Rule

Because of the powerful and fantastic performance of quantum computation, some researchers have begun considering the implications of quantum computation on the field of artificial neural networks (ANNs). The purpose of this paper is to explore a universal Hebbian-based quantum learning rule for quantum neural networks (QNNs), at the same time, we concisely testify the converging performance of this new algorithm.