Guilherme Paim

Real-Time Architecture for HEVC Motion Compensation Sample Interpolator for UHD Videos

This paper presents a high throughput architecture for a Motion Compensation (MC) sample interpolator targeting the High Efficiency Video Coding (HEVC) standard. Real-time operation and low power dissipation in video coding systems have become important research challenges, especially in mobile devices with limited computational resources and battery availability. The Fractional Motion Estimation (FME) is one of the tools in the inter-frame prediction module, which has the goal of reducing temporal redundancies by capturing motion more accurately. The Motion Compensation, responsible for compensating the motion detected at the FME process, demands the major computational effort at the decoder side and represents one of the main challenges when developing real-time HEVC decoders. The proposed architecture is able to save hardware resources through an optimized filter organization and is capable to decode UHD 4320p@60fps video sequences in real time when synthesized for the TSMC 65nm standard-cell library.

A multi-standard interpolation hardware solution for H.264 and HEVC

Attending real-time constraints in video coding systems represents a big challenge for nowadays systems, especially for high definition videos at mobile systems. The Fractional Motion Estimation (FME) and Motion Compensation (MC) are responsible for a large share of processing effort in both state-of-the-art video coding standards, the High Efficiency Video Coding (HEVC), and its predecessor, the H.264. This work proposes a multi-standard hardware solution for the fractional sample interpolation used in FME/MC processing of the HEVC and H.264 standards. The hardware design is composed of four IP (Intellectual Property) cores able to process 1080p@60fps videos independently. The whole architecture can process 2160p@60fps with 80.69mW, considering bi-prediction.

An HEVC multi-size DCT hardware with constant throughput and supporting heterogeneous CUs

This paper presents an efficient hardware design for the Discrete Cosine Transform (DCT) of High Efficiency Video Coding standard (HEVC). This hardware supports all HEVC transform sizes: 4×4, 8×8, 16×16, and 32×32 including any combination of the Transform Unit (TU) sizes. The proposed DCT architecture has a constant throughput of 32 coefficients per cycle, independently of the transform sizes combination. The architecture was synthesized for a Nangate 45nm standard-cell library and the power analysis was made considering real input vectors. The synthesis results show a very good tradeoff between area, power dissipation and processing rates. The architecture is able to process 1.6G coeff/s when running at 50MHz dissipating 24.2 mW. These results allow a processing rate of 30 HD 1080p frames per second when evaluating 17 HEVC prediction modes.

Power-efficient sum of absolute differences architecture using adder compressors

The calculation of the Sum of Absolute Differences (SAD) is one of the most time-consuming operations of the video encoder compatible with the new High Efficiency Video Coding (HEVC) standard. SAD hardware architecture employs an adder tree to accumulate the coefficients from absolute difference between two video blocks. This paper proposes the exploration of the different adder compressors structures in the SAD hardware architecture. The architectures were synthesized to 45nm standard cells. Synthesis results show that SAD architecture with adder compressors with Kogge-Stone adders in the recombination line reduces power dissipation in 60.8% on average when compared with SAD architecture using conventional adders from the synthesis tool.

Power-Efficient Sum of Absolute Differences Hardware Architecture Using Adder Compressors for Integer Motion Estimation Design

Sum of absolute differences (SAD) calculation is one of the most time-consuming operations of video encoders compatible with the high efficiency video coding standard. SAD hardware architectures employ an adder tree to accumulate the coefficients from absolute difference between two video blocks. This paper exploits different adder compressors structures into the SAD hardware architecture. The architectures were synthesized to 45-nm CMOS standard cells. Synthesis results show that SAD architecture using 8–2 compressor composed with 4–2 compressors and Kogge–Stone adder in the recombination line reduces power dissipation by 25.5% on average when compared with the SAD architecture using conventional adders from a state-of-the-art synthesis tool. Our throughput analysis shows that the designed SAD units are capable of encoding full HD (

High-throughput and memory-aware hardware of a sub-pixel interpolator for multiple video coding standards

1920\times 1080

Power efficient 2-D rounded cosine transform with adder compressors for image compression

) videos in real time at 30 frames/s.

A power-predictive environment for fast and power-aware ASIC-based FIR filter design

Real-time operation and low-power dissipation in video coding systems have become important research challenges, especially in mobile devices with limited battery and computational resources. There are many video coding standards coexisting in the market nowadays, so it is important for current devices to support different video coding standards. This paper presents a multi-standard luminance sub-samples interpolator hardware design for the Motion Compensation (MC) and Fractional Motion Estimation (FME), with support to MPEG-2/4, H.264/AVC, HEVC, and AVS/2 video coding standards. Our design is able to save hardware resources through an optimized filter organization, totally compliant with the focused standards and capable to interpolate samples for UHD 4320p@60fps at real time. The 45nm standard-cell library implementation dissipates 10mW, when processing according MPEG-2 standard, up to 46.4mW when processing AVS2.

Low power SATD architecture employing multiple sizes Hadamard Transforms and adder compressors

This work proposes a dedicated hardware design for 2-D Rounded Cosine Transform (RCT), using efficient adder compressors, and discusses comparisons with Discrete Cosine Transform (DCT). The RCT is an approximation of the cosine function, whose resultant matrix is only composed of 0 and 1 values. Therefore, the RCT can be easily implemented by using only adders/subtractors. In this work, we use combinations of efficient 4-2, 6-2 and 8-2 adder compressors for the RCT implementation. The RCT performance combined with its lower computational complexity makes this transform an excellent choice for a dedicated hardware for image compression. We present an environment, whose synthesis reports are based on a set of true images as input vectors in order to obtain valid power results. The results show that the RCT hardware solution with adder compressors minimizes both cells area and power consumption with good overall quality images.

A power-efficient 4-2 Adder Compressor topology

Nowadays, the amount of small devices performing any kind of Digital Signal Processing (DSP) has increased drastically. On the other hand, the limited energy available to such battery-powered devices is a real problem. In DSP applications, one of the most important operations is the Finite Impulse Response (FIR) filter computation. The main FIR filter characteristics are the linear phase and feed forward implementation, which make it very useful for building high stable performance filters. However, the minimal designed coefficients bit-width, in integer representation, varies for each design. The main goal of this paper is to present a power-predictive environment for fast and power-aware FIR filter design. The proposed approach searches a set of power-efficient FIR Filter during the mathematical design based on a proposed power-predictive function which is performed using both the number of taps and the bit-width of the filter. Synthesis results was performed using Cadence RTL Compiler synthesis tool for all the range of filter specifications to validate the proposed power-predictive function and the filter methodology. The main results show that the proposed power-predictive environment enables a fast and power-aware decision even in mathematical design level enabling saves in power dissipation with better filter quality, and also enabling a reduction in the time-to-market, which nowadays is a very important requirement.