Sergio Bampi

Using BDI agents to improve driver modelling in a commuter scenario

The use of multi-agent systems to model and to simulate real systems consisting of intelligent entities capable of autonomously co-operating with each other has emerged as an important field of research. This has been applied to a variety of areas, such as social sciences, engineering, and mathematical and physical theories. In this work, we address the complex task of modelling drivers’ behaviour through the use of agent-based techniques. Contemporary traffic systems have experienced considerable changes in the last few years, and the rapid growth of urban areas has challenged scientific and technical communities. Influencing drivers’ behaviour appears as an alternative to traditional approaches to cope with the potential problem of traffic congestion, such as the physical modification of road infrastructures and the improvement of control systems. It arises as one of the underlying ideas of intelligent transportation systems. In order to offer a good means to evaluate the impact that exogenous information may exert on drivers’ decision making, we propose an extension to an existing microscopic simulation model called Dynamic Route Assignment Combining User Learning and microsimulAtion (DRACULA). In this extension, the traffic domain is viewed as a multi-agent world and drivers are endowed with mental attitudes, which allow rational decisions about route choice and departure time. This work is divided into two main parts. The first part describes the original DRACULA framework and the extension proposed to support our agent-based traffic model. The second part is concerned with the reasoning mechanism of drivers modelled by means of a Beliefs, Desires, and Intentions (BDI) architecture. In this part, we use AgentSpeak(L) to specify commuter scenarios and special emphasis is given to departure time and route choices. This paper contributes in that respect by showing a practical way of representing and assessing drivers’ behaviour and the adequacy of using AgentSpeak(L) as a modelling language, as it provides clear and elegant specifications of BDI agents.

Pipelined Fast 2-D DCT Architecture for JPEG Image Compression

This paper presents the architecture and the VHDL design of a Two Dimensional Discrete Cosine Transform (2-D DCT) for JPEG image compression. This architecture is used as the core of a JPEG compressor and is the critical path in JPEG compression hardware. The 2-D DCT calculation is made using the 2-D DCT separability property, such that the whole architecture is divided into two I-D DCT calculations by using a transpose buffer. These parts are described in this paper, with an architectural discussion and the VHDL synthesis results as well. The 2-D DCT architecture uses 4,792 logic cells of one Altera Flex10kE FPGA and reaches an operating frequency of 12.2 MHz. One input block with 8/spl times/8 elements of 8 bits each is processed in 25.2 /spl mu/s and the pipeline latency is 160 clock cycles.

Run-time adaptive energy-aware motion and disparity estimation in multiview video coding

This paper presents a novel run-time adaptive energy-aware Motion and Disparity Estimation (ME, DE) architecture for Multiview Video Coding (MVC). It incorporates efficient memory access and data prefetching techniques for jointly reducing the on/off-chip memory energy consumption. A dynamically expanding search window is constructed at run time to reduce the off-chip memory accesses. Considering the multi-stage processing nature of advanced fast ME/DE schemes, a reduced-sized multi-bank on-chip memory is employed which can be power-gated depending upon the video properties. As a result, when tested for various video sequence, our approach provides a dynamic energy reduction of 82–96% for the off-chip memory and a leakage energy reduction of 57–75% for the on-chip memory compared to the Level-C and Level-C+ [7] prefetching techniques (which are the prominent data reuse and prefetching techniques in ME for video coding). The proposed ME/DE architecture is synthesized using a 65nm IBM low power technology. Compared to state-of-the-art MVC ME/DE hardware [14], our architecture provides 66% and 72% reduction in the area and power consumption, respectively. Moreover, our scheme achieves 30fps ME/DE 4-view HD1080p encoding with a power consumption of 74mW.

Dynamically reconfigurable architecture for image processor applications

This work presents an overview of the principles that underlie the speed-up achievable by dynamic hardware reconfiguration, proposes a more precise taxonomy for the execution models for reconfigurable platforms, and demonstrates the advantage of dynamic reconfiguration in the new implementation of a neighborhood image processor, called DRIP. It achieves a real-time performance, which is 3 times faster than its pipelined non-reconfigurable version.

Motion Vectors Merging: Low Complexity Prediction Unit Decision Heuristic for the Inter-prediction of HEVC Encoders

This paper presents the Motion Vectors Merging (MVM) heuristic, which is a method to reduce the HEVC inter-prediction complexity targeting the PU partition size decision. In the HM test model of the emerging HEVC standard, computational complexity is mostly concentrated in the inter-frame prediction step (up to 96% of the total encoder execution time, considering common test conditions). The goal of this work is to avoid several Motion Estimation (ME) calls during the PU inter-prediction decision in order to reduce the execution time in the overall encoding process. The MVM algorithm is based on merging NxN PU partitions in order to compose larger ones. After the best PU partition is decided, ME is called to produce the best possible rate-distortion results for the selected partitions. The proposed method was implemented in the HM test model version 3.4 and provides an execution time reduction of up to 34% with insignificant rate-distortion losses (0.08 dB drop and 1.9% bitrate increase in the worst case). Besides, there is no related work in the literature that proposes PU-level decision optimizations. When compared with works that target CU-level fast decision methods, the MVM shows itself competitive, achieving results as good as those works.

Adaptive power management of on-chip video memory for multiview video coding

An adaptive power management of on-chip video memory for Multiview Video Coding is presented. It leverages texture, motion and disparity properties of objects and their correlations in the 3D-neighborhood. It groups different Macroblocks of a frame and predicts the highly-probable motion/disparity search direction in order to power-gate idle memory regions. Exploited are the statistical properties of Macroblock groups to predict idle sectors. Our approach achieves on average 32% and 61% energy reduction (averaged over various video sequences) compared to state-of-the-art DSW [7] and Level C [12], respectively. The Motion/Disparity Estimation architecture with video memory and power management scheme is implemented using an ASIC flow (IBM-65nm Low-Power technology) and it processes 4-view HD1080p@33fps.

Design of very deep pipelined multipliers for FPGAs

This work investigates the use of very deep pipelines for implementing circuits in FPGAs, where each pipeline stage is limited to a single FPGA logic element (LE). The architecture and VHDL design of a parameterized integer array multiplier is presented and also an IEEE 754 compliant 32-bit floating-point multiplier. We show how to write VHDL cells that implement such approach, and how the array multiplier architecture was adapted. Synthesis and simulation were performed for Altera Apex20KE devices, although the VHDL code should be portable to other devices. For this family, a 16 bit integer multiplier achieves a frequency of 266 MHz, while the floating point unit reaches 235 MHz, performing 235 MFLOPS in an FPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and other considerations to apply the technique in real designs are also addressed.

Analysis and design of amplifiers and comparators in CMOS 0.35 μm technology

Abstract Design techniques and CAD tools for digital systems are advancing rapidly at decreasing cost, while CMOS analog circuit design is related mostly with the individual experience and background of the designer. Therefore, the design of an analog circuit depends on several factors such as a reliable design methodology, good modeling and technology characterization. Most of this work focuses on the analysis of several analog circuits, including their functionality, using different design methodologies. Initially the determination of two key design parameters (slope factor n and early voltage VA) and the gm/ID characteristics were derived from simulations. Then, the analysis and design of three diferent analog circuits are presented. A comparison is made between two design methodology applied to an analog amplifier design. The first one is a conventional approach where transistors are in saturation. The second one is based on the gm/ID characteristic, that allows a unified synthesis methodology in all regions of operation of the transistor. The analog modules for comparison and continuous filtering, that find vast applications today, are then analyzed and designed with the parameters and methodology proposed.

A memory aware and multiplierless VLSI architecture for the complete Intra Prediction of the HEVC emerging standard

This work proposes a hardware architecture for the Intra Frame Prediction of the emerging High Efficiency Video Coding (HEVC) standard. The architecture was designed considering all innovative features of the Intra Prediction included in the HEVC, i.e. all modes and all Prediction Units (PU) sizes. Performance and memory accesses are a problem in the HEVC intra prediction and hardware architecture designs are good alternative to solve these issues, especially when energy-efficient solutions are targeted. Buffers and internal memories were used in the designed architecture to decrease the number of external memory accesses. Two independent data paths processing eight samples in parallel and a deep and multiplierless pipeline were designed to increase the throughput. The architecture was synthesized using an IBM 65nm CMOS technology. The results have shown that the architecture is able to process 30 HD720p frames per second and 13 HD1080p frames per second when running at 500 MHz, reducing in 95% the accesses to the external memory.

A low-power memory architecture with application-aware power management for motion & disparity estimation in multiview video coding

A low-power architecture for an on-chip multi-banked video memory for motion and disparity estimation in Multiview Video Coding is proposed. The memory organization (size, banks, sectors, etc.) is driven by an extensive analysis of memory-usage behavior for various 3D-video sequences. Considering a multiple-sleep state model, an application-aware power management scheme is employed to reduce the leakage energy of the on-chip memory. The knowledge of motion and disparity estimation algorithm in conjunction with video properties are considered to predict the memory requirements of each Macroblock. A cost function is evaluated to determine an appropriate sleep mode for the idle memory sectors, while considering the wakeup overhead (latency and energy). The complete motion and disparity estimation architecture is implemented in a 65nm low power IBM technology. The experiments (for various test video sequences) demonstrate that our architecture provides up to 80% leakage energy reduction compared to state-of-the-art. Our scheme processes motion and disparity estimation of four HD1080p views encoding at 30fps with a power consumption of 57mW.