Günter Scheffler

System on silicon-IC for motion compensated scan rate conversion, picture-in-picture processing, split screen applications and display processing

An IC for consumer electronics TV sets performing 100 Hz interlaced/60 Hz progressive scan rate conversion has been designed. Picture-in-picture, split screen and picture improvement capabilities are also integrated. It applies a motion-compensating algorithm for high-quality scan rate conversion. PIP processing is done using a full frame based scan rate conversion method. Split screen applications with two asynchronous input sources are supported. All field memories are included using a high performance embedded DRAM technology. Therefore the IC, which is compatible with current TV concepts, meets economical demands with increased functionality.

New concepts on denoising and sharpening of video signals

This paper presents a new concept for improving video signals. Separating noise from the images while simultaneously sharpening these images is one key idea. The other key idea involves the serial combination of luminance transition improvement (LTI) and peaking in order to achieve the most pleasant impact on the human visual system. The different frequency channels of the video signal are thereby processed in different ways. New algorithms are presented, including LTI, contrast adaptive peaking in the case of the luminance, and chrominance transition improvement (CTI) in the case of the color components. In the case of the luminance, the LTI is used as preprocessing step for the subsequent contrast adaptive peaking. The whole image improvement concept, including all its components is to be produced as the display processor part of a new chip for double scan TV applications.

Standardized video interface eases design process and reduces time-to-market

Video ICs are composed of several signal processing units that perform different tasks such as filtering, changing the sampling rate or mixing different data streams. In most cases these blocks are connected to form a processing chain, where one block receives signals from the preceding one. To develop an IC more effectively, it is desired to reuse the known cores. The design of several video ICs in the past resulted in a lot of cores being available. The problem, however, is that all blocks are defined by their own timings which rarely fit into new surroundings. Therefore the adaptation, or even the revision of one or more blocks may become necessary. The paper describes a general approach to unify the interfaces of all video processing cores, so that a core-based design is simplified. A newly developed 100 Hz upconversion IC is presented whose processing blocks are equipped with the interface described.