Guodong Su

A 10W broadband power amplifier for base station

This paper presents the design of a broadband power amplifier with high-efficiency using silicon LDMOSFETs. With comparing frequency response of single LC matching network and two-stage one, a multiple LC matching networks composed of micro-strip lines and capacitors were adopted to enhance the bandwidth. A broadband power amplifier was implemented based on a packaged Si-LDMOS power transistor, and a saturated output power of 15 W and power gain of 14.5 dB at 1-dB compression point with maximum power-added efficiency (PAE) of 50% are demonstrated from 1.8GHz to 2.0GHz in this work.

A 60GHz power amplifier using 90-nm RF-CMOS technology

A 60GHz power amplifier (PA) is presented, using a 90-nm RF-CMOS process with 8 metal-layers. To the inductor provided by process, the Quality factor (Q value) is quite low and the model is inaccurate in millimeter-wave (MMW) design. Transmission lines (T-lines) can be modeled directly due to their inherent scalability in width and length, which is easy to realize accurate values of small reactance by T-lines. This paper uses coplanar waveguide (CPW) to realize accurate values of small reactance as well as the interconnect lines. The amplifier operates at a 1.1 V supply with 9.56 dB of power gain. The output 1dB compression point (P1dB) is +8.04 dBm with 10.2% of Power Add Efficiency (PAE), and the saturation output power (PSAT) is +11.48 dBm at 60GHz. Besides, the 3dB-band is more than 8.6 GHz (54.88 GHz-63.53 GHz). The chip occupies an area of 1099 µm × 433 µm.

A wideband LNA in 40nm CMOS

A 3-stage wideband low-noise amplifier (LNA) which operates from 45 GHz to 70 GHz is presented in this paper. A cascode amplifier with an active feedback is adopted in the first stage to realize broadband and partial noise cancelling. The capacitive cross-coupling (CCC) neutralization technology is used in the second and third stages to obtain a high gain and reverse isolation. Simulated results show that the LNA achieves 21dB gain and 6.16dB noise figure (NF) at 60 GHz. The 3-dB bandwidth is 25 GHz from 45 GHz to 70GHz, while the NF is less than 7.75dB over the entire band. The LNA is designed in 40nm CMOS process. It occupies an area of 0.99mm*0.33mm including all pads. To the authors knowledge, the proposed LNA achieves a highest bandwidth while having a comparable gain and NF in such frequency band.

A three stage, fully differential D-band CMOS power amplifier

This paper describes a 3-stage, fully differential D-band power amplifier (PA) using 0.13 μm SiGe BiCMOS technology. The fully differential common emitter (CE) configuration is adopted. The PA consists of baluns used as power splitter and combiner respectively and two simple L-type inter-stage impedance matching networks. The simulation results show that the proposed amplifier has a power gain of 12.9 dB, a saturation output power of 9.3 dBm and a peak PAE of 10.8% at 150 GHz frequency. And the output power of the PA superior to 8 dBm over the frequency range of 130-170 GHz. The power consumption is 56 mW and the designed PA size is as compact as 0.53mm×0.35mm.In this paper, the design and implementation of a three stage fully differential D-band power amplifier in 65nm CMOS technology is demonstrated. By using the capacitive neutralization technology and inter-stage matching networks based on transformers, this power amplifier achieves a peak power gain of 16.8dB and 7.9dBm saturated output power at 140GHz. The power amplifier occupies 0.2mm2 chip area (including pads). And the power consumption is 80mW from a 1.2V supply voltage (2V for the cascode stage ).

An estimable stability method applied to power amplifier design

Stability analysis is an important issue which should be solved at the beginning of the power amplifier design. An RC feed-back network is often adopted to improve the stability of power amplifier. Through the analysis of the RC network, a novel method to estimate the RC value is presented in this paper, which facilitates circuits design. A single stage power amplifier is designed in CMOS process to verify the feasibility of this method.