Jincai Wen

A 10W broadband power amplifier for base station

This paper presents the design of a broadband power amplifier with high-efficiency using silicon LDMOSFETs. With comparing frequency response of single LC matching network and two-stage one, a multiple LC matching networks composed of micro-strip lines and capacitors were adopted to enhance the bandwidth. A broadband power amplifier was implemented based on a packaged Si-LDMOS power transistor, and a saturated output power of 15 W and power gain of 14.5 dB at 1-dB compression point with maximum power-added efficiency (PAE) of 50% are demonstrated from 1.8GHz to 2.0GHz in this work.

On-chip sub-terahertz surface plasmon polariton transmission lines with mode converter in CMOS.

An on-chip low-loss and high conversion efficiency plasmonic waveguide converter is demonstrated at sub-THz in CMOS. By introducing a subwavelength periodic corrugated structure onto the transmission line (T-line) implemented by a top-layer metal, surface plasmon polaritons (SPP) are established to propagate signals with strongly localized surface-wave. To match both impedance and momentum of other on-chip components with TEM-wave propagation, a mode converter structure featured by a smooth bridge between the Ground coplanar waveguide (GCPW) with 50 Ω impedance and SPP T-line is proposed. To further reduce area, the converter is ultimately simplified to a gradual increment of groove with smooth gradient. The proposed SPP T-lines with the converter is designed and fabricated in the standard 65 nm CMOS process. Both near-field simulation and measurement results show excellent conversion efficiency from quasi-TEM to SPP modes in a broadband frequency range. The converter achieves wideband impedance matching (<−9 dB) with excellent transmission efficiency (averagely −1.9 dB) from 110 GHz–325 GHz. The demonstrated compact and wideband SPP T-lines with mode converter have shown great potentials to replace existing waveguides as future on-chip THz interconnects. To the best of the author’s knowledge, this is the first time to demonstrate the (sub)-THz surface mode conversion on-chip in CMOS technology.

Design of Planar Dual-Band Branch-Line Coupler with π-Shaped Coupled Lines

In this paper, a planar microstrip branch-line coupler is designed to have dual-band operation. A Pi-typed structure is used in place of the conventional quarter wavelength transmission line for dual-band application. This structure consists of a pair of coupled line in which one has two ends while the other has open stubs attached to its two ends, and its circuit parameters are determined by the transmission line theory. Explicit design equations are derived using ABCD-matrix. For verification, a 3-dB branch line coupler with operating frequencies of 900 MHz and 3.5 GHz is fabricated and measured on an FR-4 printed circuit board (PCB). The simulated and measured results are in good agreement with each other.

A multi-band low-noise amplifier with MOS varactors for wireless application

This paper presents the design and simulation results of a multi-band CMOS low-noise amplifier (LNA) from 1.9GHz to 2.4GHz. Input and output impedance matching networks are achieved with extra variable capacitor controlled by the voltage. The variable capacitors used in the circuit design can make the LNA operate at some key frequency bands between 1.9GHz and 2.4GHz. The LNA is designed using IBM 90nm RF CMOS process and employs a supply voltage of 1.5V and dissipates a DC power of 15mW. The complete circuit of LNA achieves good input and output matching with S11 lower than −15dB and S22 lower than −10dB between 1.9–2.4GHz. The gain is above 10dB. And the noise figure is lower than 2dB.

A compact branch-line coupler with arbitrary power division and multi frequencies suppression

In this article, a compact uniplanar branch line coupler is designed to achieve arbitrary power division ratio and multi suppression frequencies simultaneously. By replacing conventional quarter wavelength lines with the equivalent multi T-shaped lines, the branch-line coupler could have multi frequencies suppression while maintaining the conventional performance of proposed power division ratio at the fundamental frequency. Its circuit parameters are determined by the transmission line theory, and explicit design formulas are derived by ABCD-matrix. For verification, a planar microstrip branch-line coupler is simulated, fabricated and measured. Experimental results show the suppression to be over -30 dB at 3 GHz and 4.5 GHz, while operating well at 1 GHz. The circuit area o f the prototype is only 50.4% of the conventional coupler.

A compact broadband MMIC sub-harmonic mixer using quasi-lumped transmission lines

A compact broadband monolithic microwave integrated circuit (MMIC) sub-harmonic mixer using an OMMIC 70nm GaAs mHEMT technology is demonstrated for 60GHz down-converter applications. The present mixer employs an anti-parallel diode pair (APDP) to fulfill a sub-harmonic mixing mechanism. Quasi-lumped components are employed to broaden the operational bandwidth and minimize the chip size to 1.5×0.77mm2. The conversion gain is optimized by a quasi-lumped 90? phase shift stub. Experimental results show that from 50GHz to 70GHz, the conversion gain varies between -12.1dB and -15.2dB with a LO power level of 10dBm and 1GHz IF. The LO-to-RF, LO-to-IF and RF-to-IF isolations are found to be greater than 19.5dB, 21.3dB and 25.8dB, respectively. The second harmonic component of the LO signal is suppressed. The proposed mixer has an input 1dB compression point of -2dBm and exhibits outstanding figure-of-merits.

Influences of defected ground structure on different ground planes in RF power amplifier

This paper presents the effects of defected ground structure (DGS) on different ground planes in RF power amplifiers (PAs). Two DGS patterns etched on the front and back planes of printed circuit board which are named Top-DGS and Bottom-DGS, and a thru microstrip line are manufactured and measured to compare the insert loss at the fundamental and second harmonic frequencies. In order to evaluate the effects of the Top-DGS, Bottom-DGS and without DGS on the PA, three 4W PA have been designed and measured. Measured results show that the PA with the Top-DGS can reject the second harmonic about 13dB at Pout 34.76dBm, and achieve better the output power (Pout) and power added efficiency (PAE) than the one without DGS; the one with the Bottom-DGS has the suppression of about 28dB for the second harmonic at Pout 34.21dBm, and has less the Pout and PAE for the decreased characteristic impedance (Z0) of DGS pattern.

A 60GHz power amplifier using 90-nm RF-CMOS technology

A 60GHz power amplifier (PA) is presented, using a 90-nm RF-CMOS process with 8 metal-layers. To the inductor provided by process, the Quality factor (Q value) is quite low and the model is inaccurate in millimeter-wave (MMW) design. Transmission lines (T-lines) can be modeled directly due to their inherent scalability in width and length, which is easy to realize accurate values of small reactance by T-lines. This paper uses coplanar waveguide (CPW) to realize accurate values of small reactance as well as the interconnect lines. The amplifier operates at a 1.1 V supply with 9.56 dB of power gain. The output 1dB compression point (P1dB) is +8.04 dBm with 10.2% of Power Add Efficiency (PAE), and the saturation output power (PSAT) is +11.48 dBm at 60GHz. Besides, the 3dB-band is more than 8.6 GHz (54.88 GHz-63.53 GHz). The chip occupies an area of 1099 µm × 433 µm.

An efficient 4-way-combined 291 GHz signal source with 1.75 mW peak output power in 65 nm CMOS

In this paper, an efficient 291 GHz injection-locked signal source using two power-combined of 4-cell zero-phase coupled oscillator networks (CON) is demonstrated. The proposed signal source was fabricated in a 65 nm CMOS process with core area of 0.12 mm2. The source exhibits 7.5% tuning range centered at 291 GHz or equivalently operating frequency range of 280–302 GHz. It achieves a peak output power of 1.75 mW at 291 GHz with a DC-RF efficiency of 3.09%.

Design of 60 GHz parallel coupled-line bandpass filters

The paper presents design of 60GHz parallel coupled-line filters with Chebyshev passbands. Etching limit of printed circuit board technology has been taken into account and analyzed. Three filters, the center operation frequency are all 60GHz, are designed with pre-distortion based on the law of fabrication tolerances, including two conventional parallel coupled-line filters and a V-shaped one which has the advantage of input and output at the same horizontal. The comparison, between measured results with the simulation and post-simulation results based on physical dimensions of fabricated filters covered actual etched size, is presented. It is verified that the V-shaped parallel coupled-line filter after considering fabrication tolerance has a good performance and could apply to millimeter wave system.