Guoxing Wang

Design of a high voltage stimulator chip for a stroke rehabilitation system

This paper describes the design of an 8-channel high voltage stimulator chip for rehabilitation of stroke patients through surface stimulation, which requires high stimulation currents and high compliance voltage. The chip gets stimulation control data through its Serial Peripheral Interface (SPI), and can accordingly generate biphasic stimulation currents with different amplitudes, duration, frequencies and polarities independently for each channel. The current driver is implemented with thick oxide devices with a supply voltage up to 90V. The chip is designed in a 0.35μm X-FAB high voltage process.

Development of a network FES system for stroke rehabilitation

This paper describes a Functional Electrical Stimulation (FES) system based on the distributed network structure for rehabilitation of stroke patients. This FES system performs surface stimulation to activate the nerve of paretic muscles for training stroke patients to relearn motor functions. The main components of the networked FES system include a master unit (MU), a distributed stimulation-sensor unit (DSSU), and a clinical computer. In this system, the MU can drive a set of DSSUs, which is located at the node on the distributed network structure. The MU also stores the stimulation plan of rehabilitation training prescribed by clinicians. The DSSU serves as a single channel stimulator whose current amplitude, duration and frequency can be modulated by the MU. This system has two distinctive characters. First, since a stimulator is designed as a node on the network, the number of stimulation channels could be expanded according to specific needs. Second, a sensor component can be incorporated in the DSSU to allow monitoring physiological variables. The two features of system design make the networked FES system practical and flexible in clinical applications. We have completed a prototype of system including hardware and software. The evaluation test indicates that the system performance meets design specifications.

A high‐voltage stimulation chip for wearable stroke rehabilitation systems

Summary n nIn this work, an 8-channel high-voltage (HV) stimulation chip for the rehabilitation of stroke patients through surface stimulation is presented. The chip receives control data through its serial peripheral interface and can be controlled by an external microcontroller. It can accordingly generate biphasic stimulation currents with different amplitudes, duration time, frequencies, and polarities for each channel independently. The chip was designed and fabricated using X-FAB 0.35u2009µm HV mixed-signal process. Circuits were carefully designed to ensure their operations under HVs. Our measurement results showed that a supply voltage of as high as 75u2009V can be achieved, and the current driver can generate biphasic stimuli with current amplitudes up to 4u2009mA. Copyright

A feature exploration methodology for learning based cuffless blood pressure measurement using photoplethysmography

In this work, we propose a feature exploration method for learning-based cuffless blood pressure measurement. More specifically, to efficiently explore a large feature space from the photoplethysmography signal, we have applied several analytical techniques, including random error elimination, adaptive outlier removal, maximum information coefficient and Pearsons correlation coefficient based feature assessment methods. We evaluate fifty-seven possible feature candidates and propose three separate feature sets with each containing eleven features to predict the systolic blood pressure (SBP), diastolic blood pressure (DBP) and mean blood pressure (MBP), respectively. From our experimental results on a realistic dataset, this work achieves 4.77±7.68, 3.67±5.69 and 3.85±5.87 mmHg prediction accuracy for SBP, DBP and MBP. In summary, using the proposed light-weight features, the proposed predictors can successfully achieve a Grade A in two standards proposed by the American National Standards of the Association for the Advancement of Medical Instrumentation (AAMI) and British Hypertension Society (BHS).

PTT based continuous time non-invasive blood pressure system

This paper introduces the design and implementation of non-invasive, continuous time, cuff-less, blood pressure (BP) system based on pulse transmission time delay (PTT). The wearable BP device processing and monitoring both are performed using Smartphone. The PPG sensor and the integrated ECG sensor are wireless connected to smartphone. An adaptive threshold peak detection algorithm is proposed and tested to enhance the measurement accuracy. The proposed BP system achieves a systolic BP (SBP):- 1.36±7.51 mmHg and diastolic BP (DBP):- 2.44±3.49 mmHg. A new 4-LED PPG sensor is also introduced which can save 30% power consumption and reduce the interference of motion artifact (MA).

Efficient Optical Pattern Detection for Microcavity Sensors Based Lab-on-a-Chip

A framework of optical lab-on-a-chip using porous silicon microcavity membrane is presented in this paper. With measured results of the membrane, reflectance spectra detection is designed and implemented on FPGA. We manage to detect the shift of the resonant dip to distinguish target molecule solution of different concentration. To evaluate the feasibility of lab-on-a-chip, we further model the cost and performance of on-chip optical sensors and data processing system. The novel optical lab-on-a-chip will enable detection of biological samples at a much higher sensitivity than classic electrochemical methods. The efficient detecting algorithm will ensure the speed of pattern detection even when the lab-on-a-chip system has to deal with data from multiple channels.

Incomplete electrocardiogram time series prediction

The prevalence of Big Data has led to the operation practice based on time series data from multiple sources in many practical applications. The prediction analysis of time series, a fundamental objective of time series data crunch, is an integral part for planning and decision making. However, the prediction analysis based on raw time series data is hardly satisfactory as missing values are usually involved in raw data samples, even if a collection of the existing regression models are available to handle the complete time series prediction problems. To achieve higher prediction precision with incomplete raw time series data, in this paper, we describe a new framework called ISM (Incomplete time series prediction based on Selective tensor modeling and Multi-kernel learning). ISM is composed of three steps. First, multi-source time series are fused and then a selective tensor is constructed from K most relevant raw data sets. Second, the selective tensor is further factorized by ISM with the sparsity constraint to extract the common latent factors across multiple sources. Finally, these factors serve as the training features of multi-kernel learning, which is an effective approach to build multi-source regression models. Extensive experiments on the electrocardiogram data set demonstrate that the proposed framework ISM achieves a superior performance of time series prediction with missing data.

A digital multichannel neural signal processing system using compressed sensing

This paper concerns a wireless multichannel neural recording system using a compressed sensing technique to compress the recorded data. We put forth a single and a multichannel system applying a Minimum Euclidean or Manhattan Distance Cluster-based (MDC) deterministic compressed sensing matrix. The single-channel signal processing system is composed of spike detection and data compression blocks. For the construction of the MDC matrix, the distance ź is an important parameter, which can take a value of 4 or 5. In addition, the sharing strategy is used to construct a multichannel system, and we analyze the influence of the number of the channels; scan rate on the reconstruction error, compression rate and power consumption; the influence of the signal-to-noise ratio; and reconstruction performance on neural signals. Based on the results, a 256-channel digital signal processing system, implemented in a 130-nm CMOS process, is proposed. This system has power consumption per channel of 12.5 µW and silicon area per channel of 0.03 mm2, and provides data reduction of around 90% while enabling accurate reconstruction of the original signals. We build a 256-channel digital signal processing system using CS technique.We discuss circuit implementation based on the MDC matrix for signal compression.Distance in circuit design is chosen as 4 or 5 and channel-to-scan is chosen as 4.Our system has relatively low power consumption and a small area.Reconstruction accuracy is good with a large compression rate using our system.

Low-Power, High-Data Rate 915 MHz Transceiver with Fully Passive Wake-Up Receiver for Biomedical Implants

A 915 MHz transceiver has been developed for implantable medical devices. The transceiver offers exceptionally low power consumption while providing a high data rate using injection-locked oscillator. The transceiver utilizes Frequency- Shift-Keying (FSK) modulation at a data rate of 8 Mbit/s to provide wireless link between target implantable device and a central base-station unit operating in the North American Industrial, Scientific and Medical (ISM) frequency band. The circuit features a fully passive wake-up receiver (WuRx) enabling energy harvesting from Radio Frequency (RF) input. The amplitude of the FSK RF signal is controlled low for short distance transmission to further reduce the energy consumption. The transceiver, implemented in 0.13 μm CMOS process, is built on new FSK modulation scheme and based on frequency to amplitude conversion. The WuRx achieves a sensitivity of -53 dBm while the main receiver shows -78 dBm sensitivity. Thanks to the simplified hardware, the receiver dissipates only 640 μW while the transmitter consumes 1.4 mW from 1.2 V supply voltage.

10 Gb/s 1.95 mW active cascode transimpedance amplifier for high speed optical receivers

This paper presents the design and performance of a transimpedance amplifier (TIA) for optical receivers integrated in a 130nm CMOS technology. The proposed TIA is based on common source (CS) voltage amplifier with a shunt-shunt feedback resistor using active cascode technique (CSAC-TIA). The CSAC technique succeeds to extend the bandwidth without scarifying the gain and power consumption. The presented CSAC-TIA shows a post layout simulated transimpedance gain of 56.65 dBΩ with bandwidth 7 GHz for 0.2 pF photodiode capacitance and optical sensitivity of −20.5 dBm at a BER= 10−12. The presented CSAC-TIA consumes 1.95 mW from single voltage supply of 1.5 V.