Yong Lian

A Low-Power Fast-Settling Bond-Wire Frequency Synthesizer With a Dynamic-Bandwidth Scheme

This paper presents a low-power fast-settling phase-locked loop (PLL) frequency synthesizer working at 1.72–1.74 GHz for a 100 kb/s Gaussian frequency shift keying (GFSK) based transceiver suitable for wireless sensor network (WSN) applications. We propose several new techniques for lowering the power consumption in the frequency synthesizer. Resistor-based electro-static discharge protection (ESD-P) and automatic frequency calibration (AFC) are introduced to the bond-wire voltage-controlled oscillator (VCO) to deal with the inaccuracy of bond-wire inductors and uncertain parasitics. A multi-stage power-scaling scheme is developed for classical phase-switching prescaler. A dynamic-bandwidth scheme is proposed to speed up the settling time and improve the energy efficiency in a time-division WSN system. Implemented in 0.18

A 3-Lead ECG-on-Chip with QRS Detection and Lossless Compression for Wireless Sensors

\mu{\hbox {m}}

A 2.89

CMOS technology, the measurement results show that the PLL consumes 10.6 mW under 1.8 V supply voltage and settles within 18

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W Dry-Electrode Enabled Clockless Wireless ECG SoC for Wearable Applications

including the AFC process. The phase noise is

The effects of GND electrodes in capacitive-coupling body channel communication

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A low-power robust GFSK demodulation technique for WBAN applications

89.8 dBc/Hz@10 kHz and

Racetrack Memory-Based Nonvolatile Storage Elements for Multicontext FPGAs

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A novel quasi-static channel enhancing technique for body channel communication

119.3 dBc/Hz@1 MHz under receiving (Rx) mode; from receiving (Rx) state to transmitting (Tx) state, the out-band fractional-

An energy efficient fully integrated OOK transceiver SoC for wireless body area networks

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