Guru Mathur
North Carolina State University
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Publication
Featured researches published by Guru Mathur.
Applied Physics Letters | 2002
Qiliang Li; Guru Mathur; Mais Homsi; Shyam Surthi; Veena Misra; Vladimir L. Malinovskii; Karl-Heinz Schweikart; Lianhe Yu; Jonathan S. Lindsey; Zhiming Liu; Rajeev B. Dabke; Amir A. Yasseri; David F. Bocian; Werner G. Kuhr
Self-assembled monolayers of 4-ferrocenylbenzyl alcohol attached to silicon provided the basis for electrolyte-molecule-silicon capacitors. Characterization by conventional capacitance and conductance techniques showed very high capacitance and conductance peaks near ∼0.6 V associated with charging and discharging of electrons into and from discrete levels in the monolayer owing to the presence of the redox-active ferrocenes. The reversible charge trapping of these molecules suggest their potential application in memory devices. Due to the molecular scalability and low-power operation, molecular-silicon hybrid devices may be strong candidates for next-generation electronic devices.
Applied Physics Letters | 2003
Qiliang Li; Shyam Surthi; Guru Mathur; Srivardhan Gowda; Veena Misra; Thomas A. Sorenson; Robert C. Tenent; Werner G. Kuhr; Shun-ichi Tamaru; Jonathan S. Lindsey; Zhiming Liu; David F. Bocian
Hybrid silicon capacitors have been successfully fabricated by attaching monolayers of redox-active molecules via self-assembly to ultrathin silicon dioxide layers. Capacitance, conductance, and cyclic voltammetric measurements have been used to characterize these capacitors. The presence of distinct capacitance and conductance peaks associated with oxidation and reduction of the monolayers at low gate voltages indicates discrete electron storage states for these capacitors, suggesting their feasibility in memory devices. The inherent molecular scalability and low-power operation coupled with existing silicon technology support the approach of hybrid molecule-silicon devices as a strong candidate for next generation electronic devices.
Applied Physics Letters | 2004
Qiliang Li; Shyam Surthi; Guru Mathur; Srivardhan Gowda; Qian Zhao; Thomas A. Sorenson; Robert C. Tenent; Kannan Muthukumaran; Jonathan S. Lindsey; Veena Misra
Hybrid molecule-silicon capacitors have been fabricated by the self-assembly of a monolayer of porphyrin molecules on a silicon oxide surface. The porphyrin employed [5-(4-dihydroxyphosphorylphenyl)-10,15,20-trimesitylporphinatozinc(II)] attaches to silicon oxide via a phosphonate linkage. Cyclic voltammetry current and capacitance/conductance measurements have been used to characterize the capacitors. The presence of multiple distinct peaks in current density and capacitance/conductance measurements are associated with oxidation and reduction of the molecular monolayer. The charge-storage states of the capacitor indicate applicability for use in multiple-bit memory devices.
IEEE Transactions on Nanotechnology | 2005
Guru Mathur; Srivardhan Gowda; Qiliang Li; Shyam Surthi; Qian Zhao; Veena Misra
Self-assembled monolayers of redox-active molecules were formed on varying thickness of silicon dioxide (SiO/sub 2/). Cyclic voltammetry (CyV) and impedance spectroscopy (capacitance-voltage and conductance-voltage) techniques were used to characterize these structures. The charge retention properties of these molecule-oxide-silicon capacitor structures were studied by applying oxidizing voltages in two successive CyV scans without applying a reducing voltage in between the two scans. A variation of this technique, wherein a reducing voltage is applied in the second scan, was also employed. The wait time between the two scans was varied from 0 to 300 s. The number of molecules oxidized (or reduced) in the second scan increased (or decreased) with increasing wait time, which is attributed to increasing charge leakage with increasing time. The retention properties of these structures were studied and correlated to increasing oxide thickness. It was observed that the retention times increased with increasing oxide thickness if the voltage applied during the wait time was in between the oxidation and reduction peak voltages. The molecular scalability and ability to tune the retention times by varying the oxide thickness make these Si/molecular hybrid devices attractive candidates for next-generation memory applications.
Applied Physics Letters | 2007
Srivardhan Gowda; Guru Mathur; Veena Misra
In this work, monolayers of the redox-active molecules, with cationic- accessible states, were incorporated on p- and n-type silicons of varying doping concentrations. The redox voltages and kinetics were found to be strongly dependent on the silicon doping concentrations, and ambient light in case of n-Si substrate, while there was no significant impact of substrate doping concentration or ambient light in case of p-Si substrate. These results suggest the redox energy states in the molecule align within the valence band of the silicon substrate. Based on this, a model for electronic coupling and charge transfer at the molecule-semiconductor interfaces is proposed.
international electron devices meeting | 2004
Srivardhan Gowda; Guru Mathur; Qiliang Li; Shyam Surthi; Qian Zhao; Jonathan S. Lindsey; David F. Bocian; Veena Misra
Redox-active molecular monolayers were incorporated in MOSFETs to modulate the device characteristics. The discrete molecular states were manifested in the drain current characteristics indicating the presence of distinct energy levels at room temperature.
international electron devices meeting | 2003
Srivardhan Gowda; Guru Mathur; Qihang Li; Shyam Surthi; Qian Zhao; Jonathan S. Lindsey; K. Mobley; David F. Bocian; Veena Misra
The properties of silicon in hybrid CMOS/molecular capacitors were successfully engineered to produce multiple bit and long retention-time devices. Charge storage molecules were attached to silicon substrates to produce multiple bit and long retention time characteristics that may be attractive for nanoscale high density memory applications.
Applied Physics Letters | 2005
Srivardhan Gowda; Guru Mathur; Qiliang Li; Shyam Surthi; Veena Misra
Lateral conductivity within a monolayer is a key factor in the implementation of emerging dense molecular memory devices since it determines the degree of cross talk between cells. Lateral interactions within a monolayer could also lead to loss of charge through defective sites. Existing characterization techniques are limited to probing the electrical communication between molecules and attached electrodes. In this paper we demonstrate a test structure consisting of n type and p type doped silicon islands to isolate vertical conduction from lateral conduction. This structure is a useful characterization tool for tailoring the intrinsic properties of the molecules for information storage.
international conference on nanotechnology | 2005
Guru Mathur; Srivardhan Gowda; Veena Misra
New observations showing V/sub T/-assisted reduction of redox-active molecules in hybrid silicon/molecular memory devices are reported in this paper. These devices were fabricated by incorporating functionalized ferrocene molecules on varying thickness of SiO/sub 2/ on p-Si substrates. The reduction (erase) process was found to occur at two voltages - (i) at the reduction voltage of the molecules, and (ii) at the threshold voltage (V/sub T/) of the capacitor. The former depends on the electron-tunneling rate from Si to the molecules through SiO/sub 2/, while the latter is due to the formation of an inversion layer. Increased retention times were observed for devices with thick SiO/sub 2/ due to limited reduction via step (i). This behavior can be utilized to tune the write, erase and retention properties of these hybrid memory devices.
international conference on nanotechnology | 2006
Srivardhan Gowda; Guru Mathur; Veena Misra
This paper discusses the role of asymmetric tunneling across oxide barriers in Hybrid Silicon/Molecular devices. Devices incorporating redox-active (ferrocene) molecules on silicon dioxide (SiO2) of varying thickness and Hafnium dioxide (HfO2)/SiO2stack on p-Si substrates were investigated as charge storage elements. The reduction (erase) process was found to be increasingly rate-limited as compared to oxidation (write) process with increasing SiO2thickness. This is attributed to asymmetric tunneling rates mainly due to a lower potential drop across the tunnel barrier for a given gate voltage during reduction process as compared to oxidation, resulting from higher surface potential drop in Si. Although increased SiO2thickness provides for improved retention, it severely retards write process. This can be overcome by employing asymmetric layered barrier of HfO2/SiO2which enhances effect of inherent asymmetric tunneling rates and also speeds up the write process due to higher relative permittivity and lower barrier offsets of HfO2/SiO2on Si as compared to SiO2. This behavior can be utilized to improve retention properties of these hybrid memory devices with minimal deterioration in write times.