Guru Prasad Mishra

A 2D analytical cylindrical gate tunnel FET (CG-TFET) model: impact of shortest tunneling distance

A 2D analytical tunnel field-effect transistor (FET) potential model with cylindrical gate (CG-TFET) based on the solution of Laplaces equation is proposed. The band-to-band tunneling (BTBT) current is derived by the help of lateral electric field and the shortest tunneling distance. However, the analysis is extended to obtain the subthreshold swing (SS) and transfer characteristics of the device. The dependency of drain current, SS and transconductance on gate voltage and shortest tunneling distance is discussed. Also, the effect of scaling the gate oxide thickness and the cylindrical body diameter on the electrical parameters of the device is analyzed.

Impact of technology scaling on analog and RF performance of SOI–TFET

This paper presents both the analytical and simulation study of analog and RF performance for single gate semiconductor on insulator tunnel field effect transistor in an extensive manner. Here 2D drain current model has been developed using initial and final tunneling length of band-to-band process. The investigation is further extended to the quantitative and comprehensive analysis of analog parameters such as surface potential, electric field, tunneling path, and transfer characteristics of the device. The impact of scaling of gate oxide thickness and silicon body thickness on the electrostatic and RF performance of the device is discussed. The analytical model results are validated with TCAD sentaurus device simulation results.

Performance analysis of undoped cylindrical gate all around (GAA) MOSFET at subthreshold regime

In this work the sensitivity of process parameters like channel length (L), channel thickness (tSi), and gate work function (M) on various performance metrics of an undoped cylindrical gate all around (GAA) metal-oxide-semiconductor field effect transistor (MOSFET) are systematically analyzed. Undoped GAA MOSFET is a radical invention as it introduces a new direction for transistor scaling. In conventional MOSFET, generally the channel doping concentration is very high to provide high on-state current, but in contrary it causes random dopant fluctuation and threshold voltage variation. So, the undoped nature of GAA MOSFET solves the above complications. Hence, we have analyzed the electrical characteristics as well as the analog/RF performances of undoped GAA MOSFET through Sentaurus device simulator.

Conical surrounding gate MOSFET: a possibility in gate-all-around family

In this paper a new conical surrounding gate metal-oxide-semiconductor field effect transistor (MOSFET) with triple-material gate has been proposed and verified using TCAD device simulator from Synopsis. The electrostatic performance of conical model with different tapering ratios is extensively investigated and compared with that of cylindrical model (tapering ratio TR = 1). The present model exhibits improved electrostatic behavior for an optimized tapering ratio of 0.98 as compared to the conventional cylindrical model. The results reveal that the triple-material conical model provides better ON current performance, transconductance and reduced threshold voltage. On the contrary the single-material conical model exhibits maximum / ratio, minimum OFF current and reduced subthreshold swing (SS) in comparison to other models. Thus, the conical model with optimized tapering ratio can be a possible replacement of cylindrical model for low-power and high speed application.

Implementing Taguchi and cuckoo search to optimize LAA

This paper presents a global optimization technique named as Taguchis method (TM) and an evolutionary natured-inspired metaheuristic cuckoo search (CS) optimization method and applied to linear antenna array (LAA) designed for minimum side lobe levels and nulls at the desired directions. TM was developed on the basis of the orthogonal array (OA) concept, which offers systematic and efficient characteristics which effectively reduces the number of tests required in an optimization process. Another nature-inspired evolutionary CS optimization algorithm is implemented which is capable of solving general N-dimensional, linear and nonlinear optimization problems. The Lévy flight concept of CS optimization method shows its random walk which helps to generate new solutions randomly. The array geometry synthesis is first formulated as an optimization problem with the goal of side lobe level (SLL) suppression and null prescribed placement in certain directions, and then solved by both TM and CS method. Obtained results show that the TM has the tremendous ability to converge quickly.

Performance analysis of SOI MOSFET with rectangular recessed channel

In this paper a two dimensional (2D) rectangular recessed channel–silicon on insulator metal oxide semiconductor field effect transistor (RRC-SOI MOSFET), using the concept of groove between source and drain regions, which is one of the channel engineering technique to suppress the short channel effect (SCE). This suppression is mainly due to corner potential barrier of the groove and the simulation is carried out by using ATLAS 2D device simulator. To have further improvement of SCE in RRC-SOI MOSFET, three more devices are designed by using dual material gate (DMG) and gate dielectric technique, which results in formation of devices i.e. DMRRC-SOI,MLSMRRC-SOI, MLDMRRC-SOI MOSFET. The effect of different structures of RRC-SOI on AC and RF parameters are investigated and the importance of these devices over RRC MOSFET regarding short channel effect is analyzed.

An extensive electrostatic analysis of dual material gate all around tunnel FET (DMGAA-TFET)

In the proposed work an analytical model of a p-channel dual material gate all around tunnel FET (DMGAA-TFET) is presented and its performance is compared with the conventional GAA-TFET. The electrostatic potential profile of the model is obtained using 2-D Laplaces solution in the cylindrical coordinate system. A quantitative study of the drain current has been carried out using electric field in the z-axis and tunneling path. However the potential and current analysis is prolonged to different combinations of gate length in the DMGAA-TFET model. The results show an improvement in drain current and subthreshold swing as compared to GAA-TFET, which makes this model a potential replacement for low power application. Also the effect of scaling of the gate oxide thickness and cylindrical pillar diameter on the surface potential, initial tunneling point and tunneling current are analyzed.

Tunneling path based analytical drain current model for double gate Tunnel FET (DG-TFET)

This paper presents a 2D analytical model for symmetric double gate Tunnel Field Effect transistor (DG-TFET) based on tunneling path in the channel. The potential profile is obtained by solving 2D Poissons equation in the rectangular coordinate system. The drain current is extracted by integrating the band to band tunneling generation rate, initial and final tunneling length. The primary focus is on initial tunneling length as it directly influence the drain current amplitude of the device. The DG-TFET shows ON-current improvement as compared with SG-TFET. The validation of analytical results with simulated results is done by TCAD device simulator.

Analytical modeling of work-function modulated delta doped tunnel FET to improve analog performance

In this study, an analytical model for linearly modulated work-function-based delta-doped single-gate tunnel field-effect transistor (TFET) has been developed to improve the analogue performance. The impact of delta-doped layer and linearly modulated metal gate on different analogue parameters has been investigated extensively. The insertion of heavily doped delta layer in the source region improves ON current and current switching ratio performance significantly as compared to conventional TFET. Similarly, the presence of spatially work-function modulated metal gate reduces subthreshold swing and improves I 60 performance. The distance of the delta layer from the source-channel interface is optimised to 3 nm to maximise efficiency. The proposed model exhibits much improved analogue performance as compared to conventional TFET and delta-doped TFET. Thus, the model can be viewed as one of the potential replacements for metal-oxide-semiconductor field-effect transistors in ultra-low-power applications. However, the precision of present model is corroborated by using the two-dimensional TCAD Sentaurus simulator.

RF analysis of work function modulated cylindrical surrounding gate MOSFET

The unique design along with greater accuracy in device performance has made cylindrical surrounding gate MOSFET (CSGM) a cutting edge device in the present VLSI technology. Due to its cylindrical geometry, this device provides higher packing density and higher scaling possibilities. The fabrication process of a surface channel device with proper threshold voltage (Vth) directly depends upon the work function of the gate electrode. By keeping it in mind, a work function engineering based metal gate with continuous mole fraction variation along the z-axis in a cylindrical surrounding gate MOSFET (WMCSGM) is introduced. The present WMCSGM model exhibits improved RF performance as compared to CSGM model. The RF performance of the model is extensively investigated in terms of different figure of merits such as cut-off frequency, transconductance and gate capacitance.