Gustavo E. Tellez

A VLSI artwork legalization technique based on a new criterion of minimum layout perturbation

In this paper we propose a novel VLSI artwork modification technique based on the concept of a minimum layoutperturbation. Layouts are designed so that minimum design rules must be satisfied. Often layout processes such as custom layout methodologies and design rule migration activities introduce design rule violations in layouts. A minimum layout perturbation defines a minimum cost change to a layout, such that the resulting layout satisfies all design rules. We formulate the minimum perturbation cost with the objective of preserving as much as possible the geometric and topological features of the original layout. The proposed minimum perturbation problem formulation is transformed into a linear programming problem with special structure. We exploit the structure of the problem to propose efficient algorithms that solve the problem. We also propose and implement a practical graph-based simplex algorithm, which we compare to a commercially available linear programming package, resulting in more than 40X performance improvements in some cases. Finally, the proposed methods have been implemented and used in real life problems, for example in the technology migration of data path macros and a 30O-cell gate array library.

Activity-driven clock design for low power circuits

In this paper we investigate activity-driven clock trees to reduce the dynamic power consumption of synchronous digital CMOS circuits. Sections of an activity-driven clock tree can be turned on/off by gating the clock signals during the active/idle times of the clocked elements. We propose a method of obtaining the switching activity patterns of the clocked circuits during the high level design process. We formulate three novel activity-driven problems. The objective of these problems is to minimize systems dynamic power consumption. We propose an approximation algorithm based on recursive matching to solve the clock tree construction problem. We solve the gate insertion problems with an exact algorithm employing the dynamic programming paradigm. Finally, we present experimental results that verify the effectiveness of our approach. Our work in this paper is a step in understanding how high level decisions (e.g. behavioral design) can affect a low level design (e.g. clock design).

Activity-driven clock design

In this paper, we investigate reducing the power consumption of a synchronous digital system by minimizing the total power consumed by the clock signals. We construct activity-driven clock trees wherein sections of the clock tree are turned off by gating the clock signals. Since gating the clock signal implies that additional control signals and gates are needed, there exists a tradeoff between the amount of clock tree gating and the total power consumption of the clock tree. We exploit similarities in the switching activity of the clocked modules to reduce the number of clock gates. Assuming a given switching activity of the modules, we propose three novel activity-driven problems: a clock tree construction problem, a clock gate insertion problem, and a zero-skew clock gate insertion problem. The objective of these problems is to minimize the systems power consumption by constructing an activity-driven clock tree. We propose an approximation algorithm based on recursive matching to solve the clock tree construction problem. We also propose an exact algorithm employing the dynamic programming paradigm to solve the gate insertion problems. Finally, we present experimental results that verify the effectiveness of our approach. This paper is a step in understanding how high-level decisions (e.g., behavioral design) can affect a low-level design (e.g., clock design).

Minimal buffer insertion in clock trees with skew and slew rate constraints

In this paper, we investigate the problem of computing a lower bound on the number of buffers required when given a maximum clock slew rate (or rise time) constraint and a predefined clock tree. Using generalized properties of published CMOS timing models, we formulate a novel nonlinear buffer insertion problem. Next, we derive an algorithm that bounds the capacitance for each buffer stage without sacrificing the generality of the timing models. With this capacitance bound we formulate a second linear buffer insertion problem, which we solve optimally in O(n) time. The basic formulation and algorithm are extended to include a skew upper bound constraint. Using these algorithms we propose further algorithmic extensions that allow area and phase delay tradeoffs. Our results are verified using SPICE3e2 simulations with MCNC MOSIS 2.0 /spl mu/ models and parameters. Experiments with these test cases show that the buffer insertion algorithms proposed herein can be used effectively for designs with high clock speeds and small skews.

What makes a design difficult to route

Traditionally, the goal of physical synthesis has been to produce a physical realization of the input netlist that meets its timing constraints with minimum area. However, design routability has emerged from a secondary objective to perhaps the primary objective, in no small part due to the myriad of rules and constraints that emerge with each successive technology. This work overviews the complexities with modeling congestion during physical synthesis and discusses how optimizations may be able to provide some relief.

EDA in IBM: past, present, and future

Throughout its history, from the early four-circuit gate-array chips of the late 1960s to todays billion-transistor multichip module, IBM has invested in tools to support its leading-edge technology and high-performance product development. The combination of demanding designs and close cooperation among product, technology, and tool development has given rise to many innovations in the electronic design automation (EDA) area and provided IBM with a significant competitive advantage. This paper highlights IBMs contributions over the last four decades and presents a view of the future, where the best methods of multimillion gate ASIC and gigahertz microprocessor design are converged to enable highly productive system-on-a-chip designs that include widely diverse hardware and software components.

Memory Segmentation to Exploit Sleep Mode Operation

Sleep mode operation and exploiting it to minimize the average power consumption are of great importance. In this paper, we formulate the memory segmentation/partitioning problem to exploit sleep mode operation and show that the problem is NP-complete. We present polynomial time algorithms for special classes of the problem. Some generalizations of the problem are discussed. Preliminary experiments are conducted to show the effectiveness of the algorithms and applicability of the approach. The experimental data confirm that a careful partitioning allows up to 40% more sleep time which could be exploited to minimize the average power consumption. Directions for further research in this area are presented.

GLARE: global and local wiring aware routability evaluation

Industry routers are very complex and time consuming, and are becoming more so with the explosion in design rules and design for manufacturability requirements that multiply with each technology node. Global routing is just the first phase of a router and serves the dual purpose of (i) seeding the following phases of a router and (ii) evaluating whether the current design point is routable. Lately, it has become common to use a “light mode” version of the global router, similar to todays academic routers, to quickly evaluate the routability of a given placement. This use model suffers from two primary weaknesses: (i) it does not adequately model the local routing resources, while the model is important to remove opens and shorts and eliminate DRC violations, (ii) the metrics used to represent congestion are non-intuitive and often fail to pinpoint the key issues that need to be addressed. This paper presents solutions to both issues, and empirically demonstrates that incorporating the proposed solutions within a global routing based congestion analyzer yields a more accurate view of design routability.

Unification of budgeting and placement

In this paper we present a novel formulation for thenet-based timing-driven placement problem.The new formulationperforms budgeting (net delay upper bounds) andplacement modification simultaneously thus alleviates theproblem of going back-and-forth between budgeting andplacement.An algorithm to accomplished the proposedtask is presented.The proposed algorithm uses a simulatedannealing approach and a modified graph-based simplexmethod.A general formulation of timing-sriven placementis presented.It is proved that both net-based andpath-based approaches to timing-driven placement are specialcases of a more general formulation.The proposed algorithmhas been incorporated into a (timing-driven) placementpackage.Experiments on MCNC benchmarks showstrong results.The proposed algorithm offers 54% to 68%reduction over the longest path compared with the existingalgorithms.

Design methodology for the IBM POWER7 microprocessor

The IBM POWER7® microprocessor, which is the next-generation IBM POWER® processor, leverages IBMs 45-nm silicon-on-insulator (SOI) process with embedded dynamic random access memory to achieve industry-leading performance. To deliver this complex 567-mm2 die, the IBM design team made significant innovations in chip design methodology. This paper describes the most critical methodology innovations specific to POWER7 design, which were in modularity, timing closure, and design efficiency.