John M. Cohn

Managing power and performance for system-on-chip designs using Voltage Islands

This paper discusses Voltage Islands, a system architecture and chip implementation methodology, that can be used to dramatically reduce active and static power consumption for System-on-Chip (SoC) designs. As technology scales for increased circuit density and performance, the need to reduce power consumption increases in significance as designers strive to utilize the advancing silicon capabilities. The consumer product market further drives the need to minimize chip power consumption.Effective use of Voltage Islands for meeting SoC power and performance requirements, while meeting Time to Market (TAT) demands, requires novel approaches throughout the design flow as well as special circuit components and chip powering structures. This paper outlines methods being used today to design Voltage Islands in a rapid-TAT product development environment, and discusses the need for industry EDA advances to create an industry-wide Voltage Island design capability.

Pushing ASIC performance in a power envelope

Power dissipation is becoming the most challenging design constraint in nanometer technologies. Among various design implementation schemes, standard cell ASICs offer the best power efficiency for high-performance applications. The flexibility of ASICs allow for the use of multiple voltages and multiple thresholds to match the performance of critical regions to their timing constraints, and minimize the power everywhere else. We explore the trade-off between multiple supply voltages and multiple threshold voltages in the optimization of dynamic and static power. The use of multiple supply voltages presents some unique physical and electrical challenges. Level shifters need to be introduced between the various voltage regions. Several level shifter implementations will be shown. The physical layout needs to be designed to ensure the efficient delivery of the correct voltage to various voltage regions. More flexibility can be gained by using appropriate level shifters. We discuss optimization techniques such as clock skew scheduling which can be effectively used to push performance in a power neutral way.

The A to Z of SoCs

The exploding complexity of new chips and the ever decreasing time-to-market window are forcing fundamental changes in the way systems are designed. The advent of Systems-on-Chip (SoC) based on pre-designed intellectual-property (IP) cores has become an absolute necessity for embedded systems companies to remain competitive. Designing an SoC, however, is extremely complex, as it encompasses a range of difficult problems in hardware and software design. This paper explains a wide range of SoC issues including market drivers and trends, technology and integration aspects, early architecture definition, methodology, hardware and software design and verification techniques.

Layout tools for analog ICs and mixed-signal SoCs: a survey

Layout for analog circuits has historically been a time consuming, manual, trial-and-error task. The problem is not so much the size (in terms of the number of active devices) of these designs, but rather the plethora of possible circuit and device interactions: from the chip substrate, from the devices and interconnects themselves, from the chip package. In this short survey we enumerate briefly the basic problems faced by those who need to do layout for analog and mixed-signal designs, and survey the evolution of the design tools and geometric/electrical optimization algorithms that have been directed at these problems.

A low-noise, single-photon avalanche diode in standard 0.13 μm complementary metal-oxide-semiconductor process

We present the design and characterization of a single-photon avalanche diode (SPAD) fabricated with a standard 0.13 μm complementary metal-oxide-semiconductor process. We have developed a figure of merit for SPADs when these detectors are employed in high frame-rate fluorescent lifetime imaging microscopy, which allows us to specify an optimal bias point for the diode and compare our diode with other published devices. At its optimum bias point at room temperature, our SPAD achieves a photon detection probability of 29% while exhibiting a dark count rate of only 231 Hz and an impulse response of 198 ps.

SCALE: Safe community awareness and ale rting leveraging the internet of things

We propose the Safe Community Awareness and Alerting Network (SCALE), a cyber-physical system (CPS) leveraging the pervasive Internet of Things (IoT) to extend a smarter, safer home to all residents at a low incremental cost. SCALE uses novel networking technologies, commodity sensor devices, cloud services, and middleware abstractions to sense, analyze, and act on sensed events in a distributed manner. It monitors environmental factors (i.e. smoke, explosive gas) and automatically alerts residents via phone upon discovery of a possible emergency, enabling them to confirm the event and contact emergency dispatchers with minimal effort. This article describes the inception, design, development, and deployment of a prototype system to achieve these goals. We discuss lessons learned and future directions for general CPS/IoT platforms.

There is life left in ASICs

Standardcellshavelongbeenanexcellentabstractionoftechnology. ASIC design styles allowed logic designers toveryrapidlytakeadvantageofmajor advantagesinsilicontechnology. For the last few years however, many peoplehavebeenpredictingthedeathofASICs. Theyarguethatthey are too difficult to design, that the gap between theprocess technology and theASICis growing, andthat thecostwillmakethemeconomicallyinfeasible. Inthispresen-tation we will argue that there is a lot of life left in yourASIC.Specifically,thereisstillplentyofroomforimprove-mentindesigntoolstoensurewestayclosetoMoore’scurveindesignperformancedespitebaseprocesstechnologyslow-down. Similarly,costcanbeloweredsignificantlybybetteroptimization,analysisandverification.AlternativeslikeFPGAsorfullyprogrammablestandardproducts have been proposed. However, both are signifi-cantly more inefficient in their use of power than ASICs,anddonotmeetperformancerequirementsformanyappli-cations underapowerbudget. Sincefew attractivesiliconimplementationalternativesareavailabletostandardcells,itisimportantthatthedesigntoolswillstepuptothetask.

Kids today! Engineers tomorrow?

Often, it takes tough times to bring about change. We are facing a unique and daunting set of challenges, both as an industry and as a species. As a profession, we are in danger of becoming less relevant to the next generation who would carry on for us. If we are going to turn this situation around, we need to work quickly to change the conversation from one that focuses on what makes our profession difficult, to one that stresses passion, creativity, and social impact. This change could hardly be occurring at a more important time. Our planet is now facing an unprecedented global crises with many implications to the health and well-being of all people. Our skills and technology are going to be the single most important tools we have to minimize suffering and strife in light of the environmental changes that may occur. We have a wonderful opportunity right now to use our new messages to ignite the passions of the next generation of engineers across the world. It is a tough job, but it is also an immensely rewarding and fun job. So get right to it! We need to leave this world in good hands … and you are the only ones who can make that happen!

Roundtable: Design and CAD Challenges for Leading-Edge Multimedia Designs

Multimedia, game, and entertainment devices have pushed the leading edge of performance, complexity, power, form factor, design cycle time, and other key aspects of ASIC design for the past several technology nodes. This roundtable brings together experts who are defining the next generation of gaming, mobile-TV, digital-home, display, and multimedia-processing platforms. The discussion spans the underlying chip architectures and roadmaps, as well as the key design, technology, and market challenges for next-generation products.

An integrated zigbee transmitter and DC-DC converter on 0.18μm HV RF CMOS technology

A System-On-Chip (SOC) demonstrator integrating a low-noise IEEE 802.15.4 Transmitter and a DC-DC converter on a 0.18um High Voltage (HV) and RF CMOS process is presented in this paper. Noise isolation performance is critical to success of this type of SOC. A complete direct conversion transmitter was designed and various Quadrature VCO topologies were analyzed and compared based on the phase noise performance, device reliability, design robustness and image rejection. The final QVCO used in the transmitter has a FOM of 187dB, leading to an overall phase noise of -123dBc/Hz at 1MHz offset. The deep Nwell from HVCMOS process can be effectively used to provide isolation between the circuit blocks with measured results showing a sufficient noise isolation between the sensitive RF circuit and the switching 10MHz DC-DC converter.