Guy P. Lavallee

Arrays of Cu2+ -complexed organic clusters grown on gold nano dots

Controlled growth of organic multilayers from periodic gold dot arrays on SiO2 surfaces has been used to create complex overlayer structures. Nanosphere lithography (NSL) was first used to produce uniform metal patterns with particle sizes of 40 nm, spaced by gaps of 80 nm. These particles served as the nucleation centers for layer-by-layer growth of organic/metal ion complexes. The resulting structures can either be isolated adsorbed dot structures on a continuous surface or continuous networks of the adsorbed materials with isolated arrays of SiO2 surface dots. Step-by-step organic multilayer growth from small isolated centers enables us to monitor each process step by direct surface imaging techniques. Further metal evaporation and lift-off of the organic layers creates star-shaped gold structures within the original array.

Indium arsenide (InAs) single and dual quantum-well heterostructure FinFETs

This work presents experimental demonstration of InAs single and dual quantum well (DQW) heterostructure FinFETs (FF) and their superior performance over In_0.7Ga_0.3As QW FF. Peak mobility of 3,531 cm²/V-sec and 3,950 cm²/V-sec are obtained for InAs single QW FF and InAs DQW FF, respectively, at a fin width (W_fin) of 40nm and L_G = 2μm. Peak g_m of 480 μS/μm, 541 μS/um; I_DSAT of 121 μA/μm, 135 μA/μm; and SS_SAT of 101 mV/dec,103 mV/dec is demonstrated for single and DQW FF, respectively, at L_G=300nm (V_D = 0.5V, I_OFF=100 nA/μm). Finally, InAs DQW is shown to be a viable alternate channel for high aspect ratio n-channel FinFET.

Phase-Transition-FET exhibiting steep switching slope of 8mV/decade and 36% enhanced ON current

Vanadium dioxide (VO2), which exhibits electrically induced abrupt insulator-to-metal phase transition (IMT), is monolithically integrated with Silicon MOSFET to demonstrate a steep-slope (sub-kT/q) Phase-Transition FET (Phase-FET). The Phase-FET exhibits switching-slope (SS) of 8mV/decade leading to 36% increase in ON current (ION) over baseline MOSFET. We analyze the electrical characteristics of several threshold-switching materials with enhanced resistivity ratios (>105) beyond VO2 and harness them to enhance the performance of 14nm node FinFETs. Our analysis shows that up to 2.9× increase in ION, and 1.86× reduction in energy at (iso-delay) for an 11 stage ring oscillator (RO) is achievable with Phase FETs using Cu-doped HfO2 threshold switches.

Impact of Sidewall Passivation and Channel Composition on In x Ga 1- x As FinFET Performance

We experimentally demonstrate InxGa1-xAs FinFET devices with varying indium composition and quantum confinement effect. While increasing indium content enhances drive current by increasing the injection velocity, increasing quantum confinement enhances the drive currents by significantly improving the short-channel effects. Further, improved sidewall passivation using an in situ plasma nitride passivation process provides additional improved subthreshold behavior. Competitive drive currents are obtained with FinFETs realized through a scaled fin pitch process allowing 10-fins/μm layout width at a fin width of 20 nm. We report field effect mobility from multifin split-capacitance-voltage (split-CV) measurements having peak mobility of 3480 cm2/V·s for a 10-nm QW FinFET with 70% indium. Peak transconductance (gmmax) of 1.62 mS/μm, normalized to circumference, is demonstrated for devices with LG=120 nm.

Investigation of In x Ga 1−x As FinFET architecture with varying indium (x) concentration and quantum confinement

In_xGa_1-xAs FinFETs with varying indium percentage, x, and vertical body thicknesses, are fabricated in a closely packed fin configuration (10 fins per micron of layout area) and their relative performance analyzed and benchmarked. In_0.7Ga_0.3As quantum well FinFET (QWFF) exhibits peak field effect mobility of 3,000 cm²/V-sec at a fin width of 38nm with highest performance. Short channel In_0.7Ga_0.3As QWFF (L_g=120nm) exhibits I_DSAT of 1.16mA/μm at V_G-V_T=1V and extrinsic peak g_m=1.9mS/μm at V_DS=0.5V and I_OFF=30 nA/μm. Components of external resistance (R_Ext), side wall DIT, fin profile are analyzed to investigate feasibility of In_xGa_1-xAs FinFET for beyond 10nm technology node.