Nidhi Agrawal

Impact of Transistor Architecture (Bulk Planar, Trigate on Bulk, Ultrathin-Body Planar SOI) and Material (Silicon or III–V Semiconductor) on Variation for Logic and SRAM Applications

The need to enhance transistor performance below 22-nm node has brought in a change in transistor architecture from planar bulk to either ultrathin-body SOI (UTB SOI) or 3-D trigate transistors. Further improvement in transistor performance at sub-7-nm node is likely to require replacement of silicon channel with high-mobility compound semiconductor (III-V) materials. This paper presents a numerical 3-D simulation study of process variation and sidewall roughness/surface roughness effects on 3-D trigate (tapered and rectangular cross sections) on bulk and UTB SOI devices. We also investigate the effects of variation on future III-V trigate transistors using the same 3-D TCAD scheme. The results show that the threshold voltage variation value, ΔVT, in rectangular Si trigate and UTB SOI due to all the variation sources are 13.1 and 24.6 mV, respectively. Moreover, between Si and III-V compound semiconductors, the In0.53Ga0.47As trigate shows 1.5 times lower total ΔVT value making it a promising candidate for Si replacement. A Monte Carlo study of 6T SRAM cell with fin width or body thickness variation show that the 3σ value of read static noise margin [3σ (RSNM)] is least in SRAMs with rectangular Si trigate. This paper also shows that a 6T SRAM cell at different VCC shows that a Si trigate has VCCmin below 0.4 V.

Electron transport in multigate In x Ga 1-x as nanowire FETs: from diffusive to ballistic regimes at room temperature.

The III-V semiconductors such as In x Ga 1-x As (x = 0.53-0.70) have attracted significant interest in the context of low power digital complementary metal-oxide-semiconductor (CMOS) technology due to their superior transport properties. However, top-down patterning of III-V semiconductor thin films into strongly confined quasi-one-dimensional (1D) nanowire geometries can potentially degrade the transport properties. To date, few reports exist regarding transport measurement in multigate nanowire structures. In this work, we report a novel methodology for characterizing electron transport in III-V multigate nanowire field effect transistors (NWFETs). We demonstrate multigate NWFETs integrated with probe electrodes in Hall Bridge geometry to enable four-point measurements of both longitudinal and transverse resistance. This allows for the first time accurate extraction of Hall mobility and its dependence on carrier concentration in III-V NWFETs. Furthermore, it is shown that by implementing parallel arrays of nanowires, it is possible to enhance the signal-to-noise ratio of the measurement, enabling more reliable measurement of Hall voltage (carrier concentration) and, hence, mobility. We characterize the mobility for various nanowire widths down to 40 nm and observe a monotonic reduction in mobility compared to planar devices. Despite this reduction, III-V NWFET mobility is shown to outperform state-of-the-art strained silicon NWFETs. Finally, we demonstrate evidence of room -temperature ballistic transport, a desirable property in the context of short channel transistors, in strongly confined III-V nanowire junctions using magneto-transport measurements in a nanoscale Hall-cross structure.

Impact of Variation in Nanoscale Silicon and Non-Silicon FinFETs and Tunnel FETs on Device and SRAM Performance

One of the key challenges in scaling beyond 10-nm technology node is device-to-device variation. Variation in device performance, mainly threshold voltage, VT, inhibits VCC scaling. In this paper, we present a comprehensive study of process variations and sidewall roughness (SWR) effects in silicon (Si) bulk n-/p-FinFETs, In0.53Ga0.47As bulk n-FinFETs, germanium (Ge) bulk p-FinFETs, and gallium antimonide-indium arsenide (GaSb-InAs) staggered-gap heterojunction n-/p-tunnel FETs (HTFETs) using 3-D Technology Computer Aided Design numerical simulations. According to the sensitivity study, FinFET and tunnel FET (TFET) device parameters are highly susceptible to fin width, WFIN, and ultrathin body thickness, Tb, variations, respectively. TFETs show higher variation in device performance than FinFETs. A Monte Carlo study of SWR variation on nand p-FinFETs shows higher 3σ(VT Lin) of In0.53Ga0.47As bulk nand Ge bulk p-FinFETs than their Si counterparts. Furthermore, to study the variation impact on memory circuits, we simulate 6T and 10T static random access memory (SRAM) cells with FinFETs and HTFETs, respectively. The probability distribution of read failure in SRAM cells at different supply voltages, VCC, shows that HTFETs require 10T SRAM cell architecture and less than 4% variation in Tb for their VCCmin to approach 200 mV.

Indium arsenide (InAs) single and dual quantum-well heterostructure FinFETs

This work presents experimental demonstration of InAs single and dual quantum well (DQW) heterostructure FinFETs (FF) and their superior performance over In_0.7Ga_0.3As QW FF. Peak mobility of 3,531 cm²/V-sec and 3,950 cm²/V-sec are obtained for InAs single QW FF and InAs DQW FF, respectively, at a fin width (W_fin) of 40nm and L_G = 2μm. Peak g_m of 480 μS/μm, 541 μS/um; I_DSAT of 121 μA/μm, 135 μA/μm; and SS_SAT of 101 mV/dec,103 mV/dec is demonstrated for single and DQW FF, respectively, at L_G=300nm (V_D = 0.5V, I_OFF=100 nA/μm). Finally, InAs DQW is shown to be a viable alternate channel for high aspect ratio n-channel FinFET.

Tunnel junction abruptness, source random dopant fluctuation and PBTI induced variability analysis of GaAs0.4Sb0.6/In0.65Ga0.35As heterojunction tunnel FETs

We present reliability analysis of the two most critical interfaces in III-V Heterojunction Tunnel FET (HTFET) design: (1) Tunnel Heterojunction is characterized in three-dimensional atomic scale resolution using Atom Probe Tomography. We explore the impact of tunnel junction abruptness and source dopant fluctuations on HTFET performance; (2) Extremely scaled Hi-K gate dielectric (sub-0.8 nm EOT: HfO2, HfO2-ZrO2 bilayer, and ZrO2)/ III-V channel interface is evaluated using Positive Bias Temperature Instability (PBTI) measurements. HfO2 based HTFET exhibits superior PBTI performance over ZrO2 based HTFET and shows lifetime improvement over III-V FinFET.

Impact of Varying Indium(x) Concentration and Quantum Confinement on PBTI Reliability in In x Ga 1-x As FinFET

In this letter, we present a comparative study of positive bias temperature instability (PBTI) reliability in In_xGa_1-xAs FinFET with varying Indium (x=0.53 , 0.70) percentage and quantization [bulk, quantum well (QW)]. Due to lower effective transport mass and higher injection velocity, In_0.7Ga_0.3As QW FinFET provides better performance than In_0.53Ga_0.47As bulk FinFET. However, stronger quantization lowers the effective barrier height between the carriers and defect density in the oxide causing degraded PBTI reliability in the former. Our preliminary PBTI stress study shows that In_0.7Ga_0.3As QW FinFETs may need to operate at a gate overdrive of 0.1 V (i.e., near threshold operation) to meet 10 years of reliability specifications at 85 °C.

Investigation of In x Ga 1−x As FinFET architecture with varying indium (x) concentration and quantum confinement

In_xGa_1-xAs FinFETs with varying indium percentage, x, and vertical body thicknesses, are fabricated in a closely packed fin configuration (10 fins per micron of layout area) and their relative performance analyzed and benchmarked. In_0.7Ga_0.3As quantum well FinFET (QWFF) exhibits peak field effect mobility of 3,000 cm²/V-sec at a fin width of 38nm with highest performance. Short channel In_0.7Ga_0.3As QWFF (L_g=120nm) exhibits I_DSAT of 1.16mA/μm at V_G-V_T=1V and extrinsic peak g_m=1.9mS/μm at V_DS=0.5V and I_OFF=30 nA/μm. Components of external resistance (R_Ext), side wall DIT, fin profile are analyzed to investigate feasibility of In_xGa_1-xAs FinFET for beyond 10nm technology node.

Analysis of local interconnect resistance at scaled process nodes

A detailed analysis of local interconnect resistance with process scaling to 5 nm technology node is presented for both SD and DD interconnects. W M0 and Contact are identified as key resistance contributors at 5 nm process. Introducing a lower resistivity W for metal fill in M0 and Contact shows 43% reduction in M0/M1 resistance along with 5% gain in ION which are significant for ultra-low Vcc based 5 nm process.

Reduction of charge transfer region using graphene nano-ribbon geometry for improved complementary FET performance at sub-micron channel length

In this work, we investigate the effect of nano-ribbon geometries on graphene device performance and explain its effect on reducing the negative impact of Dirac point shift due to charge transfer into the graphene channel from the metal-graphene contact thereby leading to improved device performance and balanced n, p FET performance at submicron channel lengths.

Electron trapping dominance in strained germanium quantum well planar and FinFET devices with NBTI

We perform a comparative study of Negative Bias Temperature Instability (NBTI) reliability on compressively strained Germanium (s-Ge) Quantum Well (QW) Planar and FinFET p-type devices. We see electron trapping from the gate electrode in all these devices with applied negative stress. FinFETs show less ΔVT than Planar but with 1.8 times higher stress time exponent (n) and slower recovery rate than Planar. Also, Δgm/gm0 of FinFETs improves with increasing stress.