H.B Lo

Correlation between hot-carrier-induced interface states and GIDL current increase in n-MOSFET's

Correlation between created interface states and GIDL current increase in n-MOSFETs during hot-carrier stress is quantitatively discussed. A trap-assisted two-step tunneling model is used to relate the increased interface-state density (/spl Delta/D/sub it/) with the shift in GIDL current (/spl Delta/I/sub d/). Results show that under appropriate drain-gate biases, the two-step tunneling is so dominant that /spl Delta/I/sub d/ is insensitive to temperatures up to about 50/spl deg/C. With the help of 2-D device simulation, the locations of the drain region with significant two-step tunneling and the energy levels of the traps involved can be found, with both depending on the drain voltage. From these insights on /spl Delta/D/sub it/, /spl Delta/I/sub d/ and their relation, /spl Delta/D/sub it/ near the midgap can be estimated, with an error less than 10% as compared to the results of charge-pumping measurement on the same transistors. Devices with nitrided gate oxide, different gate-oxide thicknesses and different channel dimensions are also tested to verify the above correlation.

Carbon-doped GaInP/GaAs heterojunction bipolar transistors grown by metalorganic chemical vapor deposition using nitrogen as the carrier gas

The use of nitrogen as the carrier gas in metalorganic chemical vapor deposition (MOCVD) for the growth of carbon-doped GaInP/GaAs heterojunction bipolar transistors (HBTs) is reported. The material quality grown using a nitrogen carrier gas is the same as that of using a hydrogen carrier gas. High carbon doping and hole concentrations of 3×1020 and 2×1020 cm−3 in GaAs were obtained. The fabricated HBTs showed very good DC and RF performances indicating that nitrogen can be a promising carrier gas for MOCVD growth.

A reliability comparison of InGaP/GaAs HBTs with and without passivation ledge

Abstract InGaP/GaAs heterojunction bipolar transistors (HBTs) with and without passivation ledge in the extrinsic base region were investigated. Gummel plot changes before and after reliability testing were compared. The experimental results demonstrated that the devices featuring the lower quality of the extrinsic base surface are more sensitive to a temperature–current stress. The HBTs with a passivation ledge have an activation energy of 1.41 eV and a mean time to failure (MTTF) of 106 h whereas the HBTs without passivation ledge have an activation energy of 1.24 eV and a MTTF of 105 h.

Kinetics of Thermal Oxidation of 6H Silicon Carbide in Oxygen Plus Trichloroethylene

In this work, the behaviors of the trichloroethylene (TCE) thermal oxidation of 6H silicon carbide (SiC) are investigated. The oxide growth of 6H SiC under different TCE concentrations (ratios of TCE to O 2 ) follows the linear-parabolic oxidation law derived for silicon oxidation by Deal and Grove, J. Appl. Phys., 36 (1965). The oxidation rate with TCE is much higher than that without TCE and strongly depends on the TCE ratio in addition to oxidation temperature and oxidation time. The increase in oxidation rate induced by TCE is between 2.7 and 67% for a TCE ratio of 0.001-0.2 and a temperature of 1000-1150°C. Generally, the oxidation rate increases quickly with the TCE ratio for a TCE ratio less than 0.05 and then gradually saturates for a ratio larger than 0.05. The activation energy E B / A of the TCE oxidation for the TCE ratio range of 0.001-0.2 is 1.04-1.05 eV, which is a little larger than the 1.02 eV of dry oxidation. A two-step model for the TCE oxidation is also proposed to explain the experimental results. The model points out that in the SiC oxidation with TCE, the products (H 2 O and Cl 2 ) of the reaction between TCE and O 2 can speed up the oxidation, and hence, the oxidation rate is highly sensitive to the TCE ratio.

Quality improvement of low-pressure chemical-vapor-deposited oxide by N2O nitridation

Quality of low-pressure chemical-vapor-deposited (LPCVD) oxide and N2O-nitrided LPCVD (LN2ON) oxide is investigated under high-field stress conditions as compared to thermal oxide. It is found that LPCVD oxide has lower midgap interface-state density Dit-m and smaller stress-induced Dit-m increase than thermal oxide, but exhibits enhanced electron trapping rate and degraded charge-to-breakdown characteristics, which, however, are significantly suppressed in LN2ON oxide, suggesting effective elimination of hydrogen-related species. Moreover, LN2ON oxide shows further improved Si/SiO2 interface due to interfacial nitrogen incorporation.

Modeling of current gain's temperature dependence in heterostructure-emitter bipolar transistors

The temperature dependence of the current gain is investigated for GaAs-based heterostructure-emitter bipolar transistors (HEBTs). With the separation of the p-n junction and the heterojunction, the mechanism of hole injection from the base to emitter in the HEBT is different from that of a conventional HBT. Theoretical results demonstrate that the thermionic emission current plays an important role for the hole current which results in a smaller negative or even positive temperature coefficient for the current gain. Experimental data show that the base current for HEBTs is indeed dominated by thermionic emission as predicted. This finding indicates that the HEBT structure is the suitable choice for high power and high speed applications.

THERMAL EFFECT ON CURRENT GAINS OF AN ALGAAS/GAAS HETEROSTRUCTURE-EMITTER BIPOLAR TRANSISTOR

The temperature effect on current gains is presented for an AlGaAs/GaAs heterostructure-emitter bipolar transistor (HEBT). Experimental results show that the HEBT has much less temperature sensitivity in current gain than a heterojunction bipolar transistor. The current gains for the HEBT are almost constant with the substrate temperature at a high current regime. This indicates that the HEBT could be a good candidate for power applications.

Off-state gate current with quasi-zero temperature coefficient in n-MOSFETs with reoxidized nitrided oxide as gate dielectric

Temperature stability of off-state gate current (Ig) for n-MOSFETs with reoxidized nitrided oxide (RNO) as gate dielectrics prepared by rapid thermal processing is investigated. A significant phenomeon that Ig remains almost unchanged at elevated temperature is observed. This could be attributed to the fact that reoxidation recovers part of the nitridation-induced lowering of barrier height for hole emission at the RNO/Si interface, resulting in the increases of the hot-hole injection which nearly compensate the decrease of hole generation at elevated temperature in the avalanche regime. The finding reveals a useful behavior with temperature-insensitive off-state gate current for RNO devices requiring a thermally stable operation.

Suppression of hot-carrier-induced degradation in n-mosfets at low temperatures by N2O-nitridation of gate oxide

Abstract Hot-carrier effects of N 2 O-nitrided (N2ON) n -MOSFETs at low temperature are investigated under maximum substrate- and gate-current stresses, respectively. The results are compared to those of thermal-oxide (OX) n -MOSFETs. It is found that like the characteristics at room temperature, hot-carrier-induced degradations are greatly suppressed in N2ON devices relative to OX devices under the two stresses, suggesting excellent low-temperature hot-carrier reliability due to nitrogen incorporation at/near the Si–SiO 2 interface. For an OX device at low temperature, maximum gate-current stress exerts a stronger influence on its transconductance, threshold voltage and subthreshold swing than maximum substrate-current stress, and a two-piece model is used to explain the phenomena. Moreover, less shallow-trap generation observed in the N2ON device than in the OX device at low temperature is also attributed to the role of N 2 O nitridation.

Greatly suppressed stress-induced shift of GIDL in N2O-based n-MOSFET's

Abstract Considerably suppressed gate-induced drain leakage (GIDL) shifts of N 2 O-based n-MOSFETs after hot-carrier stress with different gate voltages are observed. The mechanisms involved are studied by dividing gate-oxide traps into sub-interface and bulk-oxide traps, and by means of computer simulations on electric-field distribution and carrier filling of these traps. It is demonstrated that sub-interface and bulk-oxide hole detrapping during stressing are mainly responsible for the respective GIDL shifts under two different stress conditions of V G =0.5 V D and V G = V D , with the effect of the former larger than the latter. In view of this, it is proposed that MOSFETs with N 2 O-nitrided or especially N 2 O-annealed NH 3 -nitrided gate oxide have not only fewer pre-existing sub-interface and bulk-oxide hole traps, but also greatly suppressed generation of hole and neutral electron traps due to the formation of a nitrogen-rich layer near the SiO 2 /Si interface through N 2 O treatment.