H. Børli

Precise Modeling Framework for Short-Channel Double-Gate and Gate-All-Around MOSFETs

A precise modeling framework for short-channel nanoscale double-gate (DG) and gate-all-around (GAA) MOSFETs is presented. For the DG MOSFET, the modeling is based on a conformal mapping analysis of the potential distribution in the device body arising from the interelectrode capacitive coupling, combined with a self-consistent procedure to include the effects of the inversion charge. The DG interelectrode coupling, which dominates the subthreshold behavior of the device, can also be applied with a high degree of precision to the cylindrical GAA MOSFET by performing a simple geometric scaling transformation to account for the difference in gate control in the two devices. Near threshold, self-consistent procedures invoking Poissons equation in combination with boundary conditions and suitable modeling expressions for the potential are applied to the two devices. In strong inversion, these solutions converge to those of the respective long-channel devices. The drain current is calculated as part of the self-consistent treatment. The results for both the electrostatics and the current are in excellent agreement with numerical simulations.

Compact subthreshold current and capacitance modeling of short-channel double-gate MOSFETs

A precise two-dimensional subthreshold current and capacitance modeling of short-channel, nanoscale double-gate MOSFETs is presented. The model covers a wide range of geometries and material combinations. The subthreshold model is based on conformal mapping techniques. The results are in excellent agreement with numerical simulations.

Modeling, verification and comparison of short-channel double gate and gate-all-around MOSFETs

Models for short-channel DG and GAA MOSFETs are presented. In the subthreshold regime, the electrostatics of the device is dominated by the capacitive coupling between the electrodes, which is analyzed by conformal mapping techniques. In the strong inversion regime, the device behavior is dominated by the inversion charge, allowing a 1D analysis. The models are verified by comparison with numerical device simulations. The electrostatic properties of the DG and GAA are compared, demonstrating the superior short-channel behavior of the GAA design.

Physics based current and capacitance model of short-channel double gate and gate-all-around MOSFETs

We present a precise two-dimensional current and capacitance model for nanoscale double gate and gate-all-around MOSFETs covering a wide range of operating regions, geometries and material combinations. The modeling in the sub-threshold regime is based on conformal mapping techniques. In moderate to strong inversion, we obtain self-consistent results based on the 2D Poissonpsilas equation. The results are in excellent agreement with numerical simulations.

Physics based modelling of short-channel nanowire MOSFET

A modelling framework for short channel nanowire (NW) MOSFETs that covers a wide range of operating conditions is presented. The device electrostatics in the subthreshold regime is dominated by the inter-electrode capacitive coupling, which, in the case of double gate (DG) devices, is analyzed in terms of conformal mapping techniques. Previously, we have shown that these results can also be successfully applied to the NW MOSFET, by performing an appropriate mapping to compensate for the difference in gate control between the two devices. Near and above threshold, the influence of the electronic charge is taken into account in a precise, self-consistent manner by combining suitable model expressions with Poissons equation. The models are verified by comparison with numerical device simulations.

Current and capacitance modeling of short-channel DG MOSFETs

We present a precise two-dimensional current and capacitance modeling for nanoscale double-gate MOSFETs covering a wide range of operating regions, geometries and material combinations. The modeling in the sub-threshold regime is based on conformal mapping techniques. In moderate to strong inversion, we obtain self-consistent results based on the 2D Poissons equation. The results are in excellent agreement with numerical simulations.

Physics based current and capacitance modeling of short-channel double gate MOSFETs

We present a 2D physically based compact model of the Double Gate MOSFET, with emphasis on short-channel devices of nanoscale dimensions. A framework model of the drain current modeling has been discussed for the DG device [1-3] and is now expanded to also include the device capacitances. In the sub-threshold regime of a lightly doped DG MOSFET, the electrostatics is dominated by the capacitive coupling between the electrodes. In this regime of operation, the electrostatics of the device can be approximated by the Laplace equation, which can be analytically solved using conformal mapping techniques [1,2]. From this analytical solution, we can calculate the perpendicular electric field along the gate, source and drain electrodes. The electrode charge is found by integrating the perpendicular electrical field along the desired electrode. Finally, the trans-capacitances are obtained from the derivative of the charges with respect to the electrode potentials for all combinations of electrodes and applied potentials at the four terminals. Near and above threshold, the influence of the electronic charge on the electrostatics and the electrode charges is taken into account in a precise, self-consistent manner by combining suitable model expressions with the 2D Poisson’s equation in the device body [3,4]. In this process, the quasi-Fermi potential and the drain current are determined assuming a drift-diffusion transport formalism with constant mobility. For the device considered, this was justified by comparisons with numerical simulations using both hydrodynamic and energy balance transport formalisms. Since short-channel effects are inherently contained in this analysis, no adjustable parameters are needed. The modeling framework covers the full range of bias voltages from subthreshold to strong inversion. The device considered has a gate length of 25 nm and a silicon thickness of 12 nm, permitting the use of classical electron statistics. The device electrostatics, the drain current, and the capacitances calculated from the present models compare very well with numerical simulations using the Atlas device simulator from Silvaco, see figures 1-4.