Udit Monga

Compact Subthreshold Current Modeling of Short-Channel Nanoscale Double-Gate MOSFET

A physics-based compact subthreshold current model for short-channel nanoscale double-gate MOSFETs is presented. The potential is modeled using conformal mapping techniques in combination with parabolic approximations. For subthreshold conditions, we have assumed that the electrostatics is dominated by capacitive coupling between the body electrodes. Hence, the potential is obtained as an analytical solution of the 2-D Laplace equation. The current modeling is based on drift-diffusion theory. The modeling results are in good agreement with those of numerical simulations without the use of adjustable parameters.

Compact subthreshold current and capacitance modeling of short-channel double-gate MOSFETs

A precise two-dimensional subthreshold current and capacitance modeling of short-channel, nanoscale double-gate MOSFETs is presented. The model covers a wide range of geometries and material combinations. The subthreshold model is based on conformal mapping techniques. The results are in excellent agreement with numerical simulations.

Assessment of NBTI in Presence of Self-Heating in High-

We have experimentally investigated the threshold voltage shift due to negative bias temperature instability (NBTI). The NBTI stress in the absence of self-heating (SH) is performed at two different temperatures, i.e., <i>T</i> = 25°C and 125°C, at bias conditions: gate voltage <i>V</i>_gs = -2& V and drain voltage <i>V</i>_ds = 0 V. To evaluate the effect of NBTI in the presence of SH, the stress is performed at room temperature and at <i>V</i>_gs = -2 V and <i>V</i>_ds = -1 V. It has been observed that NBTI in the presence of SH causes a significant shift in the threshold voltage.

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In this letter, we present an experimental evaluation of self-heating (SH) effects (SHEs) using S-parameter measurements for both n- and p-type SOI FinFETs. It is revealed that NFETs show a stronger SHE than PFETs, which ultimately leads to a higher variation of the intrinsic gain in NFETs. Our results also show that long-channel devices typically used in analog design show pronounced negative output conductance, which consequently leads to a negative intrinsic gain at low frequencies. Another implication of the strong SHE is that the interdie variability of the isothermal intrinsic gain gets “amplified” at lower frequencies due to SH.

SOI FinFETs

An analytical model is presented for the 3D subthreshold electrostatics of low-doped gate-all-around MOSFETs with circular and square cross sections. The model is based on a solution of the 3D Laplace equation utilizing the high symmetry of the devices and assuming near-parabolic potential distributions in the directions perpendicular to the gates for the central regions. To account for short-channel effects, additional functional forms are used near source and drain. High precision is made possible by utilizing auxiliary boundary conditions obtained from a conformal mapping analysis. Combining this model with a long-channel approximation for strong inversion, the drain current in the full range of bias voltages is calculated. The model compares very well with numerical calculations obtained from the ATLAS device simulator.

Impact of Self-Heating in SOI FinFETs on Analog Circuits and Interdie Variability

A quantum ballistic model for cylindrical nanowire MOSFETs operating in the subthreshold regime is presented. For subthreshold conditions, we have assumed that the electrostatics is dominated by the inter-electrode capacitive coupling between the body electrodes. Hence, the charge is neglected in Poissons equation, thus decoupling the quantum effects and the electrostatics in the body. Assuming cylindrical symmetry, the body potential can be obtained to a good precision by considering a 2D solution of the Laplace equation for the symmetry plane containing the cylinder axis. For this, a suitable geometric transformation is needed to account for the added gate control associated with a cylindrical gate.

Unified analytical modeling of GAA nanoscale MOSFETs

An analytical model of electrostatics and drain current for quadruple-gate MOSFET operating in the subthreshold regime is presented. The model is based on conformal mapping techniques and it captures the 3D electrostatics in the device body. We basically solve the electrostatics for practically undoped body, and thus both depletion charges and free charge carriers are neglected, thus allowing us to solve the Laplace equation in the subthreshold regime. We extend 2D conformal mapping techniques to the 3D device using appropriate scaling lengths. The obtained model has been verified by 3D numerical simulations from the ATLAS device simulator by Silvaco.

Modelling of quantum ballistic cylindrical nanowire MOSFETs in the subthreshold regime

A compact analytical model is presented for the 3D electrostatics of nanoscale gate-all-around MOSFET with a square and rectangular cross sections perpendicular to the source-drain axis. The model is based on solutions of the 3D Laplace equation (subthreshold) and Poissons equation (above threshold), where suitable 2D isomorphic modeling functions are utilized to describe the potential distribution in the cross sections. From this, the device capacitances and the drain current can be calculated in the full range of bias voltages. The model compares well with numerical calculations obtained from the ATLAS device simulator. This model can be readily extended to include double gate and trigate MOSFETS and FinFETs.

Modeling of electrostatics and drain current in nanoscale quadruple-gate MOSFET using conformal mapping techniques

A comprehensive modeling framework for 3D multigate FETs (MugFETs), applicable to FinFETs as well as gate-all-around MugFETs is presented. We use the double-gate FinFET as our reference device and solve the 2D-Laplace equation with the help of conformal mapping techniques. The 2D solution is then extended to 3D structures with the appropriate use of characteristic lengths. The results have been validated with 3D TCAD simulations from ATLAS device simulator. In addition DC-measurements on trigate SOI FinFETs for different fin width have been performed with special emphasis on the subthreshold and linear current regime behaviour. Our measured results agree reasonably well with the model.

Compact unified modeling of multigate MOSFETs based on isomorphic modeling functions

Various physics based modeling schemes for multigate MOSFETs are presented. In all cases, the models are derived from an analysis of the device body electrostatics in terms of two- or three-dimensional Laplaces and Poissons equations, where short-channel and scaling effects are implicitly accounted for. Thus a comprehensive modeling framework is derived for the subthreshold electrostatics of double-gate MOSFETs based on a conformal mapping analysis of the potential distribution in the device body arising from the inter-electrode capacitive coupling. This technique is also applied to the circular gate-all-around MOSFET by utilizing the symmetry properties of this device. For both these devices, the modeling is extended to include the strong inversion regime by a self-consistent procedure that simultaneously allows the calculation of the quasi-Fermi potential distribution, the drain current, and the intrinsic capacitances. In an alternative modeling framework, covering a wide range of multigate devices in...