H. De Man

Joint compensation of IQ imbalance and frequency offset in OFDM systems

Zero-IF receivers are gaining interest because they enable low-cost WLAN OFDM terminals. However, zero-IF receivers introduce IQ imbalance which may have a huge impact on performance. Rather than increasing component cost to decrease the IQ imbalance, an alternative is to tolerate the IQ imbalance and compensate it digitally. Current solutions converge too slowly for bursty WLAN communication. Moreover, the tremendous impact of a frequency offset on the IQ estimation/compensation problem is not considered. We analyze joint IQ-CFO estimation/compensation and propose a low-cost, highly effective compensation scheme. For large IQ imbalance (/spl epsi/=10%, /spl Delta//spl phi/=10/spl deg/) and large frequency offset, our solution results in an average remaining degradation below 0.5 dB compared to the reference case without IQ imbalance or frequency offset. It therefore enables the design of low-cost, low-complexity WLAN OFDM receivers.

Adaptive loading for OFDM/SDMA-based wireless networks

The two major obstacles toward high-capacity indoor wireless networks are distortion due to the indoor channel and the limited availability of bandwidth which necessitates a high spectral efficiency. A combined orthogonal-frequency division multiplexing/spatial-diversity multiple access (OFDM/SDMA) approach can effectively tackle both obstacles. The channel distortion due to multipath propagation is easily mitigated with OFDM while the bandwidth efficiency can be increased with the use of SDMA. In order to keep the networks cost acceptable, simplified SDMA processors are preferred over the exponentially complex optimal maximum-likelihood processors. However, these simplified processors perform significantly worse than the optimal ones in terms of average bit error rate (BER). In this paper, we show that by adapting the constellation sizes applied on the individual subcarriers to the channel conditions, the performance of OFDM/SDMA processors can be significantly enhanced. In the uplink, we derive simple closed-form equations for the optimal constellation sizes for both a simple linear minimum mean-square error (MMSE) detector and for a nonlinear MMSE decision feedback equalizer (DFE) detector. Furthermore, for each detector, we introduce a simplified loading algorithm which lowers the computational and signaling complexity substantially at a small performance penalty. In the downlink, we study the dual precoders of the uplink detectors, respectively, the linear MMSE precoder and the nonlinear Tomlinson-Harashima (TH) MMSE-based precoder. For both precoders, we derive expressions for the optimal and the simplified constellation sizes. Additionally, we show that in time-division duplexing systems, the constellation distribution of a set of dual detectors/precoders is identical for up- and downlink, which effectively halves the computational complexity of adaptive loading. In the fully loaded uplink, the proposed adaptive loading algorithm results in a gain of 9 dB for a BER=10/sup -3/ for the linear MMSE detector and a gain of 4.5 dB for the nonlinear MMSE-DFE detector. In the fully loaded downlink, a gain of 6.3 dB is achieved for the MMSE precoder and 5.5 dB for the TH-MMSE precoder.

A scalable 8.7nJ/bit 75.6Mb/s parallel concatenated convolutional (turbo-) CODEC

A 6 to 75.6Mb/s turbo CODEC with block size from 32 to 432, code rate from 1/3 to 3/4, 5.35/spl mu/s/block decoding latency and up to 8.25dB coding gain is described. This IC is fabricated in a 0.18/spl mu/m process and has a core area of 7.16mm/sup 2/. Energy-optimized architecture reduces the energy per bit to 8.7nJ and is almost constant over the throughput range.

80-Mb/s QPSK and 72-Mb/s 64-QAM flexible and scalable digital OFDM transceiver ASICs for wireless local area networks in the 5-GHz band

With the advent of mobile communications, voice telecommunications became wireless. Future applications, however, target multimedia, messaging, and high-speed Internet access, all expressing the need for a broadband high-speed wireless access technique. Both the domestic multimedia and the wireless local area network (WLANs) business markets are addressed. Established systems deliver 2-11 Mb/s based on spectrally inefficient spread-spectrum techniques, where scalability has reached a limit. The next generation of modems requires spectrally more efficient low-power and highly integrated solutions. We describe here the design of two digital baseband orthogonal frequency division multiplex (OFDM) signal processing ASICs, implementing respectively a quaternary phase-shift keying (QPSK)-based 80-Mb/s and a 64 quadrature amplitude modulation (QAM)-based 72-Mb/s digital inner transceiver. The latter partially matches the Hiperlan/2 and IEEE 802.11a standards. Joint development of signal processing algorithms and architectures along with on-chip data transfer, control, and partitioning leads to a low-power, yet flexible and scalable implementation. Both ASICs were designed in a unique object-oriented C++ design flow starting from algorithm level. The ASICs were successfully tested in a 5-GHz testbed both for file data transfer and web-cam multimedia transmission.

Constrained least squares detector for OFDM/SDMA-based wireless networks

The two major obstacles toward high-capacity indoor wireless networks are distortion due to the indoor channel and the limited bandwidth which necessitates a high spectral efficiency. A combined orthogonal frequency division multiplexing (OFDM)/spatial division multiple access (SDMA) approach can efficiently tackle both obstacles and paves the way for cheap, high-capacity wireless indoor networks. The channel distortion due to multipath propagation is efficiently mitigated with OFDM while the bandwidth efficiency can be increased with the use of SDMA. However, to keep the cost of an indoor wireless network comparable to its wired counterparts cost, low-complexity SDMA processors with good performance are of special interest. In this paper, we propose a new multiuser SDMA detector which is designed for constant modulus signals. This constrained least squares (CLS) receiver, which deterministically exploits the constant modulus nature of the subcarrier modulation to achieve better separation, is compared in terms of performance and complexity with the zero forcing (ZF) and the minimum mean square error (MMSE) receiver. Additionally, since the CLS detector relies on reliable channel knowledge at the receiver, we propose a strategy for estimating the multiple input multiple output (MIMO) channels. Simulations for a Hiperlan II-based case-study show that the CLS detector significantly outperforms the ZF detector and comes close to the performance of the MMSE detector for QPSK. For higher order M-PSK, the CLS detector outperforms the MMSF detector. Furthermore, the estimation complexity for the CLS detector is substantially lower than that for the MMSE detector which additionally requires estimation of the noise power.

Pilot-aided adaptive chip equalizer receiver for interference suppression in DS-CDMA forward link

In the forward link of DS-CDMA systems, the multipath propagation channel destroys the orthogonality of the spreading codes and therefore causes multi-user interference (MUI). Ideal non-adaptive zero-forcing (ZF) and MMSE chip equalizer receivers have been proposed to restore the orthogonality and suppress the MUI in DS-CDMA systems employing aperiodic scrambling codes. However, these receivers can only deal with slow fading multipath channels. Practical adaptive implementations of the chip equalizer receiver that can track fast fading multipath channels, are nor straightforward, since no continuous training chip sequence is available. In this paper we propose a new pilot-aided adaptive fractionally-spaced chip equalizer receiver; that is well-suited for fast fading multipath channels. By exploiting the presence of a continuous pilot signal in forthcoming third generation cellular and LEO satellite communication systems, it continuously updates at the symbol rate using a simple NLMS or a more advanced RLS adaptive scheme. The proposed receiver out-performs the RAKE receiver with perfect channel knowledge over a wide range of normalized Doppler spreads, with a complexity that is still independent of the number of users.

A single-carrier frequency-domain SDMA basestation

Two major technical challenges in the design of future broadband wireless networks are the impairments of the propagation channel and the need for spectral efficiency. We previously proposed a combined OFDM/SDMA approach that mitigates the channel impairments by orthogonal frequency division multiplexing (OFDM) with cyclic prefix insertion and that achieves a high spectral efficiency by space division multiple access (SDMA). However, because of the multicarrier modulation, this approach requires high-backoff power amplifiers in the analog frontend. We present a SC-FD-SDMA basestation, which avoids these expensive amplifiers by using constant-envelope single-carrier (SC) modulation and still features the advantages of frequency-domain (FD) multipath mitigation and SDMA. We pay special attention to the initialization of such basestation and its fixed point requirements, since they are critical aspects of any realistic implementation. A case-study shows how SC-FD-SDMA enables a 100 Mbps wireless LAN with a bandwidth efficiency of 8 bps/Hz and an uncoded BER of 10/sup -3/ at 13.5 dB.

Compensation of transmitter IQ imbalance for OFDM systems

Zero-IF transceivers are gaining interest because of their potential to enable low-cost OFDM terminals. However, the zero-IF architecture introduces IQ imbalance which may have a huge impact on the performance. Rather than increasing component cost to decrease the IQ imbalance, an alternative is to tolerate the IQ imbalance and compensate it digitally. Current solutions require extra analog hardware at the transmitter. We analyze transmit IQ imbalance estimation and propose a low-cost, highly effective estimation scheme, which is fully digital and located at the receiver. Performance analysis shows that this scheme can provide up to 4 dB gain while meeting the IEEE 802.11a constellation accuracy specification and more if larger IQ imbalance is present in the transmitter. It therefore enables the design of low-cost, low-complexity OFDM modems.

A robust joint linear precoder and decoder MMSE design for slowly time-varying MIMO channels

The joint linear precoder and decoder minimum mean squared error (MMSE) design represents a low complexity yet powerful solution for spatial multiplexing MIMO systems. Its performance, however, critically depends on the availability of timely channel state information (CSI) at both transmitter and receiver. In practice, the latter assumption can be severely challenged, due to channel time variations that lead to outdated CSI at the transmitter. State-of-the-art designs mistakenly use the outdated CSI to design the linear precoder and rely on the receiver to reduce the induced degradation. In this paper, we propose a robust Bayesian joint linear precoder and decoder solution that takes into account the uncertainty of the true channel, given the outdated CSI at the transmitter. We finally assess the robustness of our design to channel time variations through Monte-Carlo analysis of the systems MMSE and average bit-error rate (BER) performance.

Semi-blind space-time chip equalizer receivers for WCDMA forward link with code-multiplexed pilot

In the forward link of WCDMA systems, the multipath propagation channel destroys the orthogonality of the spreading codes and therefore causes multi-user interference (MUI). We propose new training-based and semi-blind space-time chip equalizer receivers for the forward link of WCDMA systems with a continuous code-multiplexed pilot. Both least-squares (LS) algorithms for block processing and recursive least-squares (RLS) algorithms for adaptive processing are derived. The proposed receivers can track fast fading multipath channels and outperform the RAKE receiver with perfect channel knowledge.