Marc Engels

Cycle-static dataflow

We present cycle-static dataflow (CSDF), which is a new model for the specification and implementation of digital signal processing algorithms. The CSDF paradigm is an extension of synchronous dataflow that still allows for static scheduling and, thus, a very efficient implementation of an application. In comparison with synchronous dataflow, it is more versatile because it also supports algorithms with a cyclically changing, but predefined, behavior. Our examples show that this capability results in a higher degree of parallelism and, hence, a higher throughput, shorter delays, and less buffer memory. Moreover, they indicate that CSDF is essential for modelling prescheduled components, like application-specific integrated circuits. Besides introducing the CSDF paradigm, we also derive necessary and sufficient conditions for the schedulability of a CSDF graph. We present and compare two methods for checking the liveness of a graph. The first one checks the liveness of loops, and the second one constructs a single-processor schedule for one iteration of the graph. Once the schedulability is tested, a makespan optimal schedule on a multiprocessor can be constructed. We also introduce the heuristic scheduling method of our graphical rapid prototyping environment (GRAPE).

Performance analysis of combined transmit-SC/receive-MRC

The average bit-error rate of transmit antenna selection combined with receive maximum-ratio combining is computed as a function of the transmit antenna update rate when using binary phase-shift keying in flat Rayleigh fading channels. This scheme achieves an order of diversity equal to the product of the number of transmit and receive antennas. Therefore, it can gain significant diversity benefits over traditional receive diversity schemes by distributing the antennas over the transmit and receive side.

A combined OFDM/SDMA approach

Two major technical challenges in the design of future broadband wireless networks are the impairments of the propagation channel and the need for spectral efficiency. To mitigate the channel impairments, orthogonal frequency division multiplexing (OFDM) can be used, which transforms a frequency-selective channel in a set of frequency-flat channels. On the other hand, to achieve higher spectral efficiency, space division multiple access (SDMA) can be used, which reuses bandwidth by multiplexing signals based on their spatial signature. In this paper, we present a combined OFDM/SDMA approach that couples the capabilities of the two techniques to tackle both challenges at once. We propose four algorithms, ranging from a low-complexity linear minimum mean squared error (MMSE) solution to the optimal maximum likelihood (ML) detector. By applying per-carrier successive interference cancellation (pcSIC), initially proposed for DS-CDMA, and introducing selective state insertion (SI), we achieve a good tradeoff between performance and complexity. A case study demonstrates that, compared to the MMSE approach, our pcSIC-SI-OFDM/SDMA algorithm obtains a performance gain of 10 dB for a BER of 10/sup -3/, while it is only three times more complex. On the other hand, it is two orders of magnitude less complex than the ML approach, for a performance penalty of only 2 dB.

Compensation of IQ imbalance and phase noise in OFDM systems

Nowadays, a lot of effort is spent on developing inexpensive orthogonal frequency-division multiplexing (OFDM) receivers. Especially, zero intermediate frequency (zero-IF) receivers are very appealing, because they avoid costly IF filters. However, zero-IF front-ends also introduce significant additional front-end distortion, such as IQ imbalance. Moreover, zero-IF does not solve the phase noise problem. Unfortunately, OFDM is very sensitive to the receiver nonidealities IQ imbalance and phase noise. Therefore, we developed a new estimation/compensation scheme to jointly combat the IQ imbalance and phase noise at baseband. In this letter, we describe the algorithms and present the performance results. Our compensation scheme eliminates the IQ imbalance based on one OFDM symbol and performs well in the presence of phase noise. The compensation scheme has a fast convergence and a small residual degradation: even for large IQ imbalance, the overall system performance for an OFDM-wireless local area network (WLAN) case study is within 0.6 dB of the optimal case. As such, our approach greatly relaxes the mismatch specifications and thus enables low-cost zero-IF receivers.

Training sequence versus cyclic prefix-a new look on single carrier communication

Orthogonal frequency-division multiplexing (OFDM), with the help of a cyclic prefix, enables low complexity frequency domain equalization, but suffers from a high crest factor. Single carrier with cyclic prefix (SC-CP) has the same advantage with similar performance, but with a lower crest factor and enhanced robustness to phase noise. The cyclic prefix is overhead, so we put more information in it by implementing this cyclic prefix as a training sequence (TS). This new training aided frequency domain equalized single carrier (TASC) scheme offers us additional known symbols and enables better synchronization and (potentially) channel estimation, with the same performance as SC-CP.

Cyclo-static data flow

The high sample-rates involved in many DSP-applications, require the use of static schedulers wherever possible. The construction of static schedules however is classically limited to applications that fit in the synchronous data flow model. In this paper we present cyclo-static data flow as a model to describe applications with a cyclically changing behaviour. We give both a necessary and sufficient condition for the existence of a static schedule for a cyclo-static data flow graph and show how such a schedule can be constructed. The example of a video encoder is used to illustrate the importance of cyclo-static data flow for real-life DSP-systems.

A low-complexity ML channel estimator for OFDM

Orthogonal frequency-division multiplexing with cyclic prefix enables low-cost frequency-domain mitigation of multipath distortion. However, to determine the equalizer coefficients, knowledge of the channel frequency response is required. While a straightforward approach is to measure the response to a known pilot symbol sequence, existing literature reports a significant performance gain when exploiting the frequency correlation properties of the channel. Expressing this correlation by the finite delay spread, we build a deterministic model parametrized by the channel impulse response and, based on this model, derive the maximum-likelihood channel estimator. In addition to being optimal (up to the modeling error), this estimator receives an elegant time-frequency interpretation. As a result, it has a significantly lower complexity than previously published methods.

Joint compensation of IQ imbalance and frequency offset in OFDM systems

Zero-IF receivers are gaining interest because they enable low-cost WLAN OFDM terminals. However, zero-IF receivers introduce IQ imbalance which may have a huge impact on performance. Rather than increasing component cost to decrease the IQ imbalance, an alternative is to tolerate the IQ imbalance and compensate it digitally. Current solutions converge too slowly for bursty WLAN communication. Moreover, the tremendous impact of a frequency offset on the IQ estimation/compensation problem is not considered. We analyze joint IQ-CFO estimation/compensation and propose a low-cost, highly effective compensation scheme. For large IQ imbalance (/spl epsi/=10%, /spl Delta//spl phi/=10/spl deg/) and large frequency offset, our solution results in an average remaining degradation below 0.5 dB compared to the reference case without IQ imbalance or frequency offset. It therefore enables the design of low-cost, low-complexity WLAN OFDM receivers.

Grape-II: a system-level prototyping environment for DSP applications

We propose a rapid-prototyping setup to minimize development cost and a structured-prototyping methodology to reduce programming effort. The general-purpose hardware consists of commercial DSP processors, bond-out versions of core processors, and field-programmable gate arrays (FPGAs) linked to form a powerful, heterogeneous multiprocessor, such as the Paradigm RP developed within the Retides (Real-Time DSP Emulation System) Esprit project. Our Graphical Rapid Prototyping Environment (Grape-II) automates the prototyping methodology for these hardware systems by offering tools for resource estimation, partitioning, assignment, routing, scheduling, code generation, and parameter modification. Grape-II has been used successfully in three real-world DSP applications. >

Analysis and experimental verification of digital substrate noise generation for epi-type substrates

Substrate coupling in mixed-signal ICs can cause important performance degradation of the analog circuits. Accurate simulation is therefore needed to investigate the generation, propagation, and impact of substrate noise. Recent studies were limited to the time-domain behavior of generated substrate noise and to noise injection from a single noise source. This paper focuses on substrate noise generation by digital circuits and on the spectral content of this noise. To simulate the noise generation, a SPICE substrate model for heavily doped epi-type substrates has been used. The accuracy of this model has been verified with measurements of substrate noise, using a wide-band, continuous-time substrate noise sensor, which allows accurate measurement of the spectral content of substrate noise. The substrate noise generation of digital circuits is analyzed, both in the time and frequency domain, and the influence of the different substrate noise coupling mechanisms is demonstrated. It is shown that substrate noise voltages up to 20 mV are generated and that, in the frequency band up to 1 GHz, noise peaks are generated at multiples of the clock and repetition frequency. These noise signals will strongly deteriorate the behavior of small signal analog amplifiers, as used in integrated front-ends.