H.-J. Engelmann

Structure and thermal stability of graded Ta–TaN diffusion barriers between Cu and SiO2

Abstract Sputter deposited Ta and TaN single layers of 10 nm thickness as well as graded TaN/Ta and Ta/TaN/Ta layer stacks that act as diffusion barriers for Cu metallization were investigated after annealing at temperatures between T an =300 and 700 °C. By means of glancing angle X-ray diffraction, glow discharge optical emission spectroscopy and transmission electron microscopy, results of microstructure and phase characterization were correlated with diffusion phenomena. For the pure Ta barrier, Ta diffusion through the Cu cap layer to the sample surface is observed at T an =500 °C, and the transformation of initially grown metastable β-Ta into the equilibrium α-Ta phase occurs at T an =600 °C. In contrast, a fcc TaN layer remains stable at least up to T an =700 °C. In the case of the graded layer stacks, first signs of N diffusion out of the TaN film into the adjacent Ta layers are observed after annealing at T an =300 °C, and formation of hexagonal Ta 2 N starts at T an =500 °C. Whereas in the course of thermal treatments for the threefold graded Ta/TaN/Ta barrier all TaN reacts with Ta to form Ta 2 N, some fcc TaN remains in the twofold graded TaN/Ta barrier.

Characterization of barrier/seed layer stacks of Cu interconnects by electron tomographic three-dimensional object reconstruction

Due to the continuing downscaling of transistor and interconnect structures in microelectronic products, today only transmission electron microscopy (TEM) is capable of on-product analysis of the smallest structures with sufficient spatial resolution. However, finite specimen thickness complicates the interpretation of conventional TEM images. Electron tomographic three-dimensional object reconstruction is a promising approach to overcome this limitation. We applied this technique for the first time to characterize Cu interconnect Ta-barrier/Cu-seed layer stacks deposited under different conditions. Their roughness and step coverage becomes clearly visible in the reconstructions. Current possibilities and limitations of this technique as well as future requirements are discussed.

Measuring the dielectric constant of materials from valence EELS

Valence EELS combined with STEM provides an approach to determine the dielectric constant of materials in the optical range of frequencies. The paper describes the experimental procedure and discusses the critical aspects of valence electron energy-loss spectroscopy (VEELS) treatment. In particular, the relativistic losses might affect strongly the results, and therefore they have to be subtracted from the spectra prior the analysis. The normalization of the energy-loss function is performed assuming an uniform thickness of the investigated area, which is reasonably fulfilled for carefully prepared FIB samples. This procedure requires the presence of at least one reference material with known dielectric properties to determine the absolute thickness. Examples of measuring the dielectric constant for several materials and structures are presented.

Effect of annealing on the microstructure of ultrathin tungsten nitride diffusion barriers for copper metallization

Microstructure, phase composition and interface properties of 10- and 50-mm thick CVD-deposited W-N layers covered with Cu were investigated. Phase formation and structural changes of the layer stacks occurring at elevated temperatures (450-600 °C) were correlated. The initially amorphous barriers undergo an abrupt crystallization between 550 °C/1 h and 600 °C/1 h anneals in vacuum. Further annealing at 600 °C up to 16 h leads to changes in the layer configuration such as N redistribution and Cu agglomeration. No signs of significant Cu diffusion through the barriers were observed for the performed anneals up to 600 °C/16 h.

Cross-sectional thin film characterization of Si compounds in semiconductor device structures using both elemental and ELNES mapping by EFTEM

Abstract The ongoing scaling-down of semiconductor device structures requires new techniques for cross-sectional thin film characterization. Energy filtering transmission electron microscopy was used for both elemental mapping and electron energy-loss near edge structure (ELNES) mapping of Si compounds. Si, Si 3 N 4 and SiO 2 layers could be clearly differentiated by elemental mapping as well as by ELNES mapping. A clear differentiation of the two phases in CoSi/CoSi 2 layer stacks was only possible by ELNES mapping. It is shown that specific energy filter settings allows distinction between all the Si compounds using only the Si–L 2,3 electron energy-loss edge and the respective electron energy-loss near edge structures.

Investigation of the Influence of the Local Microstructure of Copper Interconnects on Void Formation and Evolution during Electromigration Testing

The electromigration‐induced void evolution has been investigated in‐situ on fully embedded inlaid copper test structures inside a SEM, utilizing the method described in [1]. After the failure of the test structure or after significant voiding had been observed the cathode via region of the samples was prepared for subsequent TEM and/or EBSD analysis in order to reveal the position of grain boundaries and the orientations of the grains in the neighborhood of a void. It was confirmed that intersections of grain boundaries with interfaces of the interconnect lines or clusters of small grains can act as nucleation sites for initial void formation or as trapping sites on which voids can be stopped. Furthermore, it was found that for interconnects with strengthened top interface, where the diffusion rate is significantly lower due to the changed chemical bonding, that the void movement occurs mainly along the copper/liner interface. Such interconnects show significantly longer lifetimes. In this paper, local a...

Challenges to TEM in high performance microprocessor manufacturing

Smaller structures and new materials require the application of advanced TEM techniques for process control and failure analysis in 45 nm CMOS technology node and beyond. Both imaging TEM and analytical TEM techniques have to be modified or adapted to special questions. There are several reasons for that: n nA) n nDevice structures that have to be characterized are often located completely within a TEM lamella. For example, typical gate lengths of 45 nm technology node transistors are in the range between 40 and 45 nm. The diameters of respective contacts are smaller than 80 nm. Assuming a standard lamella thickness of 60...80 nm, not all details of a 3D structure can be seen in the 2D projection image anymore. A possible approach to solve this problem is the application of Electron Tomography. While tomographic image acquisition and data treatment have already become a standard technique, sample preparation is still a challenge, especially in case of failure analysis. As an example, Figure 1 shows the 3D reconstruction of a defect in the contact area. Missing silicide caused an increased electrical resistance in that case. n n n n nB) n nThe application of new materials requires the characterization of their properties in dependence on deposition and treatment parameters. For example, low-k dielectric materials which are used to reduce the cross-talk between Cu interconnects show changes in chemical composition caused by plasma etch processes. The resulting kvalue increase has to be measured in the direct neighbourhood of etched structures like trenches and vias, with a spatial resolution better than 5 nm. While changes in chemical composition are analyzed by EELS, direct measurement of the k-value can be done by Valence EELS. A procedure was developed which allows determining the 1014 Hzfrequency dielectric permittivity [1]. Even though this is not the k-value corresponding to the GHz-frequency range used in microprocessors, relative changes in the dielectric constant can be detected very precisely (Figure 2). Ultra low-k (ULK) materials that are expected to be introduced for the 32 nm CMOS technology node will contain pores. Local pore size/pore distribution characterization will be another challenge for TEM. n n n n nC) n nThe introduction of’ strained silicon’ into the channel region of transistors requires advanced characterization techniques. Mechanical stress results in a distortion of the silicon lattice which affects the electronic band structure, allowing improvements in carrier mobility. For process control and next technology node transistor development, local strain measurements in the Si MOSFET channel are needed. Nano Beam Diffraction (NBD) is an analysis technique that uses a small probe electron beam with reduced convergence angle to produce diffraction patterns with smaller spots than in CBED patterns [2]. The lattice parameter can be determined from the positions of the spots which allows strain quantification. The challenge in this technique is the NBD pattern analysis for very precise lattice spacing determination which is needed for strain quantification. Figure 3 shows the relative change of the Si lattice spacing in direction in the channel region of a tensile strained NMOS transistor. n n n n nD) n nWith shrinking of structure sizes new questions arise regarding product reliability. For example, the Cu microstructure becomes more and more important with decreasing dimensions of the interconnect lines. Grain size, grain orientation and twin formation can influence the stability against electromigration/stress migration to a high degree. So far, the EBSD technique has been used to characterize the Cu microstructure. Since agglomerates of small Cu grains are expected to be a reliability concern for the 32 nm CMOS technology, grains with sizes below 40 nm have to be analyzed which requires a TEM-based technique. Dark-Field Diffraction Circular Scanning with subsequent diffraction pattern reconstruction can be used to produce grain orientation maps. As an example, Figure 4 shows a [001] inverse pole figure map of a Cu interconnect stack.

Impact of both metal composition and oxygen/nitrogen profiles on p-channel metal-oxide semiconductor transistor threshold voltage for gate last high-k metal gate

As transistor size continues to shrink, SiO2/polySi has been replaced by high-k/metal gate (HKMG) to enable further scaling. Two different HKMG integration approaches have been implemented in high volume production: gate first and gate last—the latter is also known as replacement gate approach. In both integration schemes, getting the right threshold voltage (Vt) for NMOS and PMOS devices is critical. A number of recent studies have shown that Vt of devices is highly dependent on not just the as deposited material properties but also on subsequent processing steps. In this work, the authors developed an advanced high-resolution electron energy loss spectroscopy method capable of accurate measurement of material composition on device structures. Using this method, the nitrogen and oxygen concentration at the HKMG interface on p-channel field-effect transistor (PFET) transistors with slightly different metal gate stacks were studied. The authors demonstrated that the correct amount of nitrogen and oxygen at...

The Evolution of Barrier Properties During Reliability Testing of Cu Interconnects

The investigation of stress‐induced voiding (SIV) is one of the key aspects to characterize metallization reliability. Typical test methodologies include the investigation of resistance shifts during temperature storage tests at temperatures between 150°u2009C to 275°u2009C. During these tests, only very small resistance increases dependent on the test structure are allowed. Physical failure analysis of such samples typically reveals voids below the vias of the test structures. However, recently we encountered unusual resistance shifts at the highest stress temperature which did not yield classical stress‐induced voiding detectable by failure analysis. We found changes in barrier integrity explaining the resistance shift by barrier oxidization. This has been verified by specially prepared material as well as extensive failure analysis investigation.

Thermal Behavior of Graded Ta‐Si/Ta‐Si‐N Diffusion Barriers for Cu Metallization

Using glancing angle X‐ray diffraction, glow discharge optical emission spectroscopy, and transmission electron microscopy, the crystallization behavior and thermal stability of graded Ta‐Si/Ta‐Si‐N diffusion barriers was analyzed after annealing at various temperatures. For a Ta30Si18N52/Ta73Si27 bilayer and a Ta73Si27/Ta30Si18N52/Ta73Si27 trilayer, nitrogen redistribution within the whole barrier is observed at Tan ⩾ 500 °C. Further heat supply leads to barrier crystallization into Ta2N. Depositing the layer stacks directly onto silicon, a critical temperature of Cu silicide formation was determined. For graded Ta‐Si/Ta‐Si‐N diffusion barriers, this temperature turned out to be between the corresponding values for Ta73Si27 and Ta30Si18N52 single layers.