Moritz-Andreas Meyer

In situ SEM observation of electromigration phenomena in fully embedded copper interconnect structures

An experimental set-up is presented, that allows in situ scanning electron microscope (SEM) investigations of the progress of electromigration damage in fully embedded copper interconnect structures. A LEO Gemini 1550 SEM has been equipped with a heating stage and electrical connections for the experiment. The studied interconnect structures are usually used for reliability testing in electromigration ovens. These test structures are located within the scribelines of wafers. Therefore, they allow the characterization of the electromigration behaviour of products on the wafer. To enable the SEM observation, focused ion beam (FIB) was used to prepare cross-sections of the samples maintaining their electrical functionality. Thereby, a thin layer of passivation was left over in front of the interconnects to keep them fully embedded. The SEM images which were taken at an angle of 60° allow the observation of both the entire via/contact and the connecting lines. Multiple images were recorded during the degradation experiments. The resulting video sequences provide a good visualization of the formation, growth and motion of voids at the stressed interconnects. The dominant diffusion path has been identified.

Investigation of the Influence of the Local Microstructure of Copper Interconnects on Void Formation and Evolution during Electromigration Testing

The electromigration‐induced void evolution has been investigated in‐situ on fully embedded inlaid copper test structures inside a SEM, utilizing the method described in [1]. After the failure of the test structure or after significant voiding had been observed the cathode via region of the samples was prepared for subsequent TEM and/or EBSD analysis in order to reveal the position of grain boundaries and the orientations of the grains in the neighborhood of a void. It was confirmed that intersections of grain boundaries with interfaces of the interconnect lines or clusters of small grains can act as nucleation sites for initial void formation or as trapping sites on which voids can be stopped. Furthermore, it was found that for interconnects with strengthened top interface, where the diffusion rate is significantly lower due to the changed chemical bonding, that the void movement occurs mainly along the copper/liner interface. Such interconnects show significantly longer lifetimes. In this paper, local a...

Electron Backscatter Diffraction: Application to Cu Interconnects in Top-View and Cross Section

EBSD has been applied to study the microstructure of copper interconnects in detail. Both, top-view and cross-section investigations were performed. FIB polishing was successfully applied to obtain cross-sections of specific structures like vias. Moreover, it has been shown that passivated test structures can be investigated. With the high spatial resolution of EBSD it also becomes possible to study nanointerconnects with critical dimension of 60 nm and below. Complex experiments can be conducted, which will improve the understanding of the microstructure evolution and the impact on performance and reliability of advanced integrated circuits.

X‐ray Microscopy Studies of Electromigration in Advanced Copper Interconnects

X‐rays have the advantage that they penetrate samples which are several micrometers thick without significant sample damage, and that they provide a chemical image contrast between different dielectric layers of the Cu/low‐k on‐chip interconnect stack. Therefore, x‐ray microscopy is an ideal tool for quantitative 3‐D investigations of void dynamics with high spatial resolution of 20 nm. Using the BESSY full‐field transmission x‐ray microscope (TXM), we performed electromigration studies of advanced backend‐of‐line (BEoL) stacks of high‐performance microprocessors containing copper interconnects and low‐k materials. We observed void movement along the top copper/dielectric (SiNx) interface which is found to be the main pathway for electromigration‐induced atomic copper transport.

Understanding the Impact of Surface Engineering, Structure, and Design on Electromigration through Monte Carlo Simulation and In‐Situ SEM Studies

The Cu dual‐damascene interconnects are investigated by studying the effects of surface engineering including surface cleaning and alloying, design including M1/M2 architectures, buried Ta layers, and interconnect tree structures through Monte Carlo simulations, TEM and in‐situ SEM. The Cu surface was treated with reducing, inert, and reactive gases to induce compositional changes at the interface capped by different layers including silicides, nitrides and their variants. In untreated samples, the asymmetry of the test structures leads to higher MTFs for the upper layer (M2) test structures, however upon surface treatments, the MTFs of lower layer (M1) test structures showed a 2× improvement and could achieve lifetimes comparable to M2 test structures. Cu‐Sn chemical bonding was introduced to the Cu/SiNx interface by immersion Sn surface treatment. This chemical force effectively blocked the dominant surface diffusion path in Cu interconnect, thus leading to 10× lifetime improvement. Failure mode changed...

Potential and Limits of Texture Measurement Techniques for Inlaid Copper Process Optimization

For future technology nodes with shrunken interconnect dimensions, a thorough texture analysis of the metal interconnects becomes increasingly important in order to optimize and to control the inlaid‐copper process. In comparison to plane metal layers deposited on wafers, the microstructure of the metal is more complicated in copper lines and vias which were produced using an inlaid process. Therefore, advanced texture‐measurement techniques like X‐ray microdiffraction, electron backscatter diffraction (EBSD), and TEM combined with automated crystallography analysis (ACT) are needed to obtain the required microstructure information. These complementary methods are suitable to pick up local as well as integral information on the crystallographic orientation of the copper interconnects and liner materials. Potential and limits of the available techniques and the respective instrumentation are discussed in this paper. Examples of process‐monitoring capabilities and of development support, especially with reg...

Microstructure Effect on Electromigration‐Induced Degradation of Inlaid Copper Interconnects

Electromigration‐induced degradation processes in via/line dual inlaid copper interconnect test structures are discussed based on experimental studies. Void formation, growth and movement, and consequently interconnect degradation, depend on both interface bonding and copper microstructure. Void movement along the copper line and void growth in the via are discontinous processes, wherein their step‐like behavior is caused by copper microstructure. Microstructure studies and microstructure monitoring are becoming more important for strengthened top interfaces of copper lines, e. g. by local alloying of the copper or by applying an additional coating on top of the polished copper lines. As a result of this interface engineering, the contribution of grain boundary diffusion becomes increasingly important for the directed mass transport and for electromigration‐induced degradation.

In situ X‐ray Microscopy Studies of Electromigration in Copper Interconnects

Real‐time X‐ray microscopy is applied for degradation studies to understand electromigration‐induced transport processes in on‐chip copper interconnects. The material transport in inlaid Cu line/via structures is observed with about 40 nm lateral resolution. The image sequences show void formation, migration and nucleation processes. Correlation of the real‐time X‐ray images with post‐mortem SEM micrographs is used to discuss degradation mechanisms in inlaid copper interconnects. Due to the high penetration power of X‐rays through matter and its high spatial resolution, X‐ray microscopy (XRM) overcomes several limitations of conventional microscopic techniques. It utilizes the natural absorption contrast between the structures of interest, i.e. for on‐chip copper interconnects embedded in dielectrics. Due to their different X‐ray absorption characteristics at 0.52 keV, even different silicon compounds like Si, SiO2, and Si3N4 can be distinguished in X‐ray images of thinned layers as demonstrated. For fail...

The Evolution of Barrier Properties During Reliability Testing of Cu Interconnects

The investigation of stress‐induced voiding (SIV) is one of the key aspects to characterize metallization reliability. Typical test methodologies include the investigation of resistance shifts during temperature storage tests at temperatures between 150° C to 275° C. During these tests, only very small resistance increases dependent on the test structure are allowed. Physical failure analysis of such samples typically reveals voids below the vias of the test structures. However, recently we encountered unusual resistance shifts at the highest stress temperature which did not yield classical stress‐induced voiding detectable by failure analysis. We found changes in barrier integrity explaining the resistance shift by barrier oxidization. This has been verified by specially prepared material as well as extensive failure analysis investigation.

Effect of Overburden Thickness on the Copper Microstructure of Dual‐Inlaid Interconnect Structures

Dual‐inlaid Cu interconnects with different overburden thicknesses were fabricated and subsequently annealed applying identical conditions. The microstructure in trenches was characterized by electron backscatter diffraction (EBSD) before and after chemical mechanical polishing (CMP). For samples subjected to CMP, grain size and texture were determined from top‐view EBSD scanning on arrays of trenches. Smaller grain size and stronger Cu (111) texture were observed in the samples with thinner overburden layer. Further EBSD investigations were carried out on cross‐sections of trenches in samples not subjected to CMP which suggested interplay of grain growth mechanism in trench and overburden.