H.-J. L. Gossmann

GaAs metal-oxide-semiconductor field-effect transistor with nanometer-thin dielectric grown by atomic layer deposition

A GaAs metal–oxide–semiconductor field-effect transistor (MOSFET) with thin Al2O3 gate dielectric in nanometer (nm) range grown by atomic layer deposition is demonstrated. The nm-thin oxide layer with significant gate leakage current suppression is one of the key factors in downsizing field-effect transistors. A 1 μm gate-length depletion-mode n-channel GaAs MOSFET with an Al2O3 gate oxide thickness of 8 nm, an equivalent SiO2 thickness of ∼3 nm, shows a broad maximum transconductance of 120 mS/mm and a drain current of more than 400 mA/mm. The device shows a good linearity, low gate leakage current, and negligible hysteresis in drain current in a wide range of bias voltage.

GaAs MOSFET with oxide gate dielectric grown by atomic layer deposition

For the first time, a III-V compound semiconductor MOSFET with the gate dielectric grown by atomic layer deposition (ALD) is demonstrated. The novel application of the ALD process on III-V compound semiconductors affords tremendous functionality and opportunity by enabling the formation of high-quality gate oxides and passivation layers on III-V compound semiconductor devices. A 0.65-/spl mu/m gate-length depletion-mode n-channel GaAs MOSFET with an Al/sub 2/O/sub 3/ gate oxide thickness of 160 /spl Aring/ shows a gate leakage current density less than 10/sup -4/ A/cm/sup 2/ and a maximum transconductance of 130 mS/mm, with negligible drain current drift and hysteresis. A short-circuit current-gain cut-off frequency f/sub T/ of 14.0 GHz and a maximum oscillation frequency f/sub max/ of 25.2 GHz have been achieved from a 0.65-/spl mu/m gate-length device.

Depletion-mode InGaAs metal-oxide-semiconductor field-effect transistor with oxide gate dielectric grown by atomic-layer deposition

Recently, significant progress has been made on GaAs metal-oxide-semiconductor field-effect transistors (MOSFETs) using atomic-layer deposition (ALD)-grown Al2O3 as gate dielectric. We show here that further improvement can be achieved by inserting a thin In0.2Ga0.8As layer as part of the channel between Al2O3 and GaAs channel. A 1-μm-gate-length, depletion-mode, n-channel In0.2Ga0.8As/GaAs MOSFET with an Al2O3 gate oxide of 160 A shows a gate leakage current density less than 10−4u2009A/cm2, a maximum transconductance ∼105 mS/mm, and a strong accumulation current at Vgs>0 in addition to buried-channel conduction. Together with longer gate-length devices, we deduce electron accumulation surface mobility for In0.2Ga0.8As as high as 660 cm2/Vu200as at Al2O3/In0.2Ga0.8As interface.

Advances in high κ gate dielectrics for Si and III-V semiconductors

Abstract Our ability of controlling the growth and interfaces of thin dielectric films on III–V semiconductors by ultrahigh vacuum deposition has led to investigations of gate stacks containing rare earth oxides of Gd 2 O 3 and Y 2 O 3 as alternative high κ gate dielectrics for Si. The abrupt interfaces achieved in these gate stacks have enabled the electrical, chemical, and structural studies to elucidate the critical materials integration issues for CMOS scaling, including morphology dependence, interfacial structure and reaction, thermal stability and gate electrode compatibility.

Impact of metal/oxide interface on DC and RF performance of depletion-mode GaAs MOSFET employing MBE grown Ga2O3(Gd2O3) as gate dielectric

Abstract Employing Ga 2 O 3 (Gd 2 O 3 ) as gate dielectric and Si-doped GaAs as conducting channel, depletion-mode GaAs MOSFETs were fabricated. DC I – V and transfer curves show no pinch-off and drain current hysteresis. Etching a thin layer from the top of Ga 2 O 3 (Gd 2 O 3 ) in the gate region before gate metal deposition leads to full pinch-off and significantly reduces the drain current hysteresis. This process may remove the contaminated Ga 2 O 3 (Gd 2 O 3 ) due to exposure to chemicals and prior processes, and thus results in a clean gate metal to oxide interface. The clean gate metal to Ga 2 O 3 (Gd 2 O 3 ) interface also leads to higher DC transconductance, higher unity current gain cut-off frequency as well as higher unity power gain cut-off frequency as compared with GaAs MOSFET devices with a contaminated metal/oxide interface at the gate.

Binding energy of vacancies to clusters formed in Si by high-energy ion implantation

Measurements of the binding energy (Eb) of vacancies to vacancy clusters formed in silicon following high-energy ion implantation are reported. Vacancy clusters were created by 2 MeV, 2×1015u2002cm−2 dose Si implant and annealing. To prevent recombination of the excess vacancies (Vex) with interstitials from the implant damage near the projected range (Rp), a Si-on-insulator substrate was used such that the Rp damage was separated from the Vex by the buried oxide (BOX). Two Vex regions were observed: one in the middle of the top Si layer (V1ex) and the other at the front Si/BOX interface (V2ex). The rates of vacancy evaporation were directly measured by Au labeling following thermal treatments at temperatures between 800 and 900u200a°C for times ranging from 600 to 1800 s. The rate of vacancy evaporation from V2ex was observed to be greater than from V1ex. The binding energy of vacancies to clusters in the middle of the silicon top layer was 3.2±0.2 eV as determined from the kinetics for vacancy evaporation.

Enhanced Low Temperature Electrical Activation of B in Si

The electrical activation of B in n-type epitaxial-Si(100) has been enhanced in the temperature range of 400–800u200a°C. This enhanced activation was measured for 40 keV, 2×1014u2009cm−2 dose of B implanted into a vacancy-rich Si region. The vacancy-rich region consists of excess vacancies (Vex) generated by a 2 MeV Si implant in the dose range of 3×1015–10×1015u2009cm−2. The B activation in vacancy-rich Si is found to be a factor of ∼2.4 larger with up to ∼80% of the B activated as compared to similar B implant and activation anneals carried out in the bulk Si. The dependence of B activation on Vex concentration shows that the active B concentration increases with the Vex concentration. From this dependence it was estimated that at least three vacancies are required to activate an additional B atom. This process is distinctly different from the low temperature activation that occurs during solid-phase epitaxial recrystallization of B-doped amorphous Si as no amorphous Si is produced during any step. This low tempera...

The effect of fluorine from BF 2 source/drain extension implants on performance of PMOS transistors with thin gate oxides

Boron penetration from the gate electrode into the Si substrate presents a significant problem in advanced PMOS device fabrication. Boron penetration, which causes a degradation of many transistor parameters, is further enhanced when BF/sub 2/ is used to dope the gate electrode. It is known that pile-up of fluorine from the BR gate implant at the polysilicon/gate oxide interface is responsible for the enhanced boron penetration. However, no reports have been made that address enhanced boron penetration due to fluorine from the source/drain (S/D) implants. It is shown here that fluorine from the S/D extension implants is also a significant problem, degrading transistor performance for gate oxide thickness less than 27 /spl Aring/ and gate lengths less than 0.5 /spl mu/m.

DC and RF characteristics of depletion-mode GaAs MOSFET employing a thin Ga/sub 2/O/sub 3/(Gd/sub 2/O/sub 3/) gate dielectric layer

DC characteristics of a depletion-mode (D-mode) GaAs MOSFET with a thin Ga/sub 2/O/sub 3/(Gd/sub 2/O/sub 3/) gate dielectric layer (74 /spl Aring/) show low gate leakage current, negligible drain current hysteresis and higher than 10 V gale-drain two-terminal breakdown voltage. Compared to MESFET with the same gate length, channel material and fabricated by the same process, the GaAs MOSFET shows higher unity current gain cutoff frequency (Ft). The higher Ft for the MOSFET than that of the MESFET agrees with earlier theoretical predictions.

GaAs-based MOSFETs with Al/sub 2/O/sub 3/ gate dielectrics grown by atomic layer deposition

In this paper, we demonstrate for the first time GaAs-based MOSFETs with excellent performance using of CVD is a very robust, highly manufacturable process.