K.K. Ng

Effects of hot-carrier trapping in n- and p-channel MOSFET's

Detailed measurements of hot-carrier gate current and its trapping effects were studied on both n- and p-channel MOSFETs down to submicrometer channel lengths. Comparison of the measurements for these two types of devices is made. No hot-hole gate current or hot-hole trapping was detected in p-channel MOSFETs. A hot-electron gate current is present not only in n-channel MOSFETs, but also in p-channel MOSFETs where the current is increased by hot-electron trapping. By trapping hot electrons uniformly over the channel in n-MOSFETs, it was shown that hot-electron trapping produces only negative oxide charge without generating interface traps.

Analysis of the gate-voltage-dependent series resistance of MOSFET's

The intrinsic parasitic series resistance that occurs near the channel end of a MOSFET is analyzed. This new model includes the effects due to the unavoidable doping gradient near the metallurgical junction. It is assumed that current first conducts through the accumulation layer before spreading into the bulk region, and thus the spreading (injection) resistance and the accumulation layer resistance have to be considered in series and both are gate-voltage dependent. More importantly, they are shown to be a strong function of the steepness of the doping profile. The model quantitatively predicts these resistance components for a given process, and it emphasizes the necessity for a steep junction profile in order to minimize the series resistance of MOSFETs.

The impact of intrinsic series resistance on MOSFET scaling

The intrinsic parasitic series resistance associated with the practical structure of a MOSFET is examined. The components considered include contact resistance, diffusion sheet resistance, spreading (injection) resistance, and accumulation layer resistance. The impact of the total resistance on MOSFET scaling is assessed, down to a channel length of 0.15 µm. The results show that, contrary to what has been claimed before, the transconductance and current of a MOSFET continue to increase as the channel length is miniaturized, although the degradation percentage-wise compared to an ideal device without series resistance continues to increase. Based on the degraded I-V characteristics and their effects on an inverter, it is shown here that for NMOS or PMOS digital circuits, the maximum degradation in speed due to series resistance is 20-35 percent compared to ideal scaling for the shortest channel considered. For CMOS circuits, the maximum degradation is reduced to 7-15 percent. In absolute terms, a loss of speed in either case due to miniaturization of channel length is not expected even down to 0.15 µm.

A comparison of majority- and minority-carrier silicon MIS solar cells

A systematic experimental investigation is reported of metal-SiO<inf>2</inf>-silicon (MIS) solar cells, as a function of SiO<inf>2</inf>thickness<tex>d</tex>, in the useful range 8 Å <<tex>d</tex>< 20 Å. Both majority-carder (Au-SiO<inf>2</inf>- nSi) and minority-carrier (Al-SiO<inf>2</inf>-pSi) structures are studied and their performance compared for SiO<inf>2</inf>layers prepared under identical oxidation conditions and with identical silicon surface treatments. The short-circuit current densities are observed to be suppressed by tunneling through the SiO<inf>2</inf>layers for<tex>d \gsim 17</tex>Å, whereas fill factors begin to decrease at even smaller values of d. The optimum effective AM1 conversion efficiencies for the majority-carrier cells are 9-10 percent for 10 Å ≲<tex>d</tex>≲ 14 Å, and for the minority-carrier cells are 11-12 percent for<tex>d \simeq 10-11</tex>Å. These results are in agreement with theoretical calculations, also presented here, which take account of both electrostatic and dynamic effects of interface states, and of their dependence on bias voltage and illumination.

On the calculation of specific contact resistivity on

In order to design submicrometer Si MOSFETs properly, the specific contact resistivity rho /sub c/ has to be controlled. The rho /sub c/ is known to be a function of both the barrier height and the Si surface doping concentration. An existing theory is used to generate rho /sub c/, emphasizing details in the practical regimes, with a careful choice of proper parameters such as the tunneling effective mass, which is a function of both temperature and doping concentration. >

Reevaluation of the ftBV/sub ceo/ limit on Si bipolar transistors

The Johnson limit predicts that due to fundamental material limitations, the f/sub t/BV/sub ceo/ product for Si bipolar transistors cannot exceed 200 GHz-V. Since this limit ignores many practical components, it should not be achievable experimentally. In light of the fact that results reaching this limit have been reported, we have reevaluated such fundamental limits, and have found that this number should be much higher.

Seeded oscillatory growth of Si over SiO2 by cw laser irradiation

Extensive seeded epitaxial growth of crystalline Si over SiO2 was achieved by an oscillatory regrowth method applied to rectangular Si pads recessed into a thick SiO2 film. Narrow (≃5 μm) via holes linked the pads with the bulk (100) Si substrate. Oriented single crystals propagated as far as 500 μm from the seeding area, following the long term advance of a scanned focused laser beam.

An improved generalized guide for MOSFET scaling

For the miniaturization of MOSFETs, a generalized guide for scaling was given by J.R. Brews et al. (see IEEE Electron Dev. Lett., vol EDL-1, p.2, 1980). This formula can be used as a good starting point before device fine tuning, and works well above 0.5 mu m in channel length. It is expected, however, that for channel lengths below 0.5 mu m, it becomes inaccurate because of the nature of the equation. The erroneous implication is that if gate oxide or junction depth approaches zero, the channel length can be reduced to zero without short-channel effects. A formula in which the functions are modified to correct this anomaly is presented. Another important improvement is that the degree of short-channel effect is left as an input variable to fit the different requirements of circuits. The revised formula has been shown to be accurate down to 0.1- mu m channel length. >

IVB-6 effects of grain boundaries on laser crystallized poly-Si MOSFETs

Laser crystallization of poly-Si on insulator yields material of X10 pm grain size, and several groups have r ported fabrication of devices in such films. The performance of these devices, while inferior to that of single-crystal devices, indicates that the presence of grain boundaries is not fatal. We have therefore examined the effects of grain boundary density in the channel of MOSFETs by studying the channel length dependence of their characteristics in laser processed material.

A high-performance directly insertable self-aligned ultra-rad-hard and enhanced isolation field-oxide technology for gigahertz silicon NMOS/CMOS VLSI

The authors describe a novel field-oxide structure for rad-hard NMOS/CMOS VLSI. This is a three-layer structure consisting of a thin thermal oxide, a doped polysilicon sheet deposited on the thin oxide, and a thick CVD (chemical-vapor-deposited) oxide layer on the polysilicon. The small effective electrical thickness of the oxide combined with the ground potential of the polysilicon enhances the radiation hardness and maintains good isolation, even at radiation levels as high as 10/sup 8/ rads and above. For 100-A gate oxide, the subthreshold leakage of a MOSFET (MOS field effect transistor) with a field shield structure is less than 10/sup -13/ A/ mu m, and the off current is less than 10/sup -12/ A/ mu m, after a total dose of 100 Mrad. This structure is self-aligned and directly insertable into submicron NMOS/CMOS VLSI without any changes in the circuit design. The circuits made with this technology can operate at 2.5-3 GHz, even after a total dose of 50-100 Mrad. >