H. O. Muller

Effects of disorder on the blockade voltage of two-dimensional quantum dot arrays

The influence of both geometric and offset charge disorder of two-dimensional quantum dot arrays (also known as network tunnel junctions) on their Coulomb blockade voltage Vb is studied using extensive Monte–Carlo simulations. A general increase of Vb with increasing disorder is confirmed, but an exception to the rule is found for intermediate degrees of offset charge disorder. Detailed studies of the Vb distribution reveal a stability of its minimal value against geometric disorder, whereas this figure is considerably increased for high offset charge disorder. Implications of our results for single electron device design are discussed.

Nanoscale Coulomb blockade memory and logic devices

This paper gives a brief review of our recent work done in the area of nanometre-scale Coulomb blockade (CB) memory and logic devices, that enable us to realize future electron-number scalability by overcoming inherent problems to conventional semiconductor devices. We introduce multiple-tunnel junctions (MTJs), naturally formed in heavily doped semiconductor nanowires, as a key building block for our CB devices. For memory applications, the hybrid MTJ/MOS cell architecture is described, and its high-speed RAM operation is investigated. For logic applications the binary decision diagram logic is discussed as a suitable architecture for low-gain MTJ transistors.

Design and analysis of high-speed random access memory with Coulomb blockade charge confinement

A silicon-based memory cell utilizing Coulomb blockade is analyzed for use as a high-speed RAM. Operation principles and design guidelines are given by simple analytical modeling and simulations. By performing transient waveform Monte Carlo simulations, high-speed write operation is demonstrated with a time shorter than 10 ns. The memory node voltage of less than 0.1 V is detected by a newly proposed split-gate cell structure with a minimum disturbance to/from nonselected cells, which indicates the compatibility of this structure with conventional field effect transistors.

High-speed single-electron memory: cell design and architecture

A new silicon-based single-electron memory cell is presented for use as a high-speed RAM. Novel architecture and operation schemes are evaluated by conducting Monte Carlo single-electron simulations. By performing transient waveform analysis, a high-speed write operation is demonstrated with a write time shorter than 10 nsec.

Simulating Si multiple tunnel junctions from pinch-off to ohmic conductance

Due to their compatibility with CMOS, multiple tunnel junctions (MTJs) are giving rise to an increasing interest in Coulomb blockade silicon devices, along with a higher demand for simulation. Whereas the operating principle has been known for a number of years, here we present new simulation results on MTJs, including geometric island size and island separation. Application of MTJ in a memory cell is discussed.

Simulation of Si multiple tunnel junctions

Single electron multiple tunnel junctions (MTJs) provide a useful means of achieving Coulomb blockade e!ects using silicon technology. A blocking dot model is developed for the simulation of these MTJs. Our simulation uses a single-electron simulator integrated into a SPICE-type conventional circuit simulator, thus allowing for the simulation of MTJ-based memory cells. ( 1999 Elsevier Science B.V. All rights reserved.

Coulomb Blockade and Disorder in 2D Quantum Dot Arrays

We investigate the influence of both size disorder and background charge disorder, on the Coulomb blockade voltage of two–dimensional arrays of metallic quantum dots for varying array size. Both the mean blockade voltage and its variation are considered for several array sizes with varying degrees of disorder. Design rules for devices using those arrays are derived.

Strategy for Off-Current Suppression in Thin-Film Transistors

Field induced trap assisted band-to-band tunneling in poly-silicon thin-film transistors is studied using a two-dimensional model. Both the space dependence and the effect of graded doping are investigated. A graded doping profile results in a moderate reduction in the current, while a much larger reduction is achieved by increasing the thickness of the gate oxide near the drain region. In this way, the on/off ratio of the thin-film transistor should be greatly improved.

Design Optimization of Coulomb Blockade Devices

We investigate the design of a Coulomb blockade device consisting of a rectangular array of quantum dots or ultrasmall metallic islands with regard to its stability against geometric size disorder and offset charges. To simulate the device operation we perform a statistical analysis of the Coulomb blockade voltage which results in practical design rules.

Simulation of high-speed single-electron memory

A novel lateral single electron memory (L-SEM) architecture and its high-speed write operation were demonstrated with a write time comparable to conventional DRAMs. Excellent subthreshold characteristics of the sense MOSFET with split gates were also presented. The robustness of the L-SEM cell structure was also discussed in terms of the offset charge issue.