H. Ribot

Chip-to-chip optical interconnections between stacked self-aligned SOI photonic chips

Photonic silicon devices are key enabling technologies for next generation High Performance Computers. In this paper, we report the possibility to stack and optically interconnect SOI based photonic chips for future System-In-Package photonic architecture. Combining vertical grating couplers and state-of-the-art flip-chip technology, we demonstrated low loss penalties and wide spectral range optical interconnections between stacked photonic chips.

A Fluxless and Low-Temperature Flip Chip Process Based on Insertion Technique

For heterogeneous materials assembly, the thermal expansion mismatch between the chip and the substrate is a roadblock for flip chip bonding of ultrafine-pitch ( les 10 mum) and large diagonal devices ( ges 20 mm). Residual strains in bumps and device warpage have been calculated to evaluate the thermomechanical limits of a conventional flip chip soldering process using micro bumping. As a solution to overcome these limits, this paper describes a new patented flip-chip technology representing a technological breakthrough compared to conventional methods such as soldering or bonding through conductive adhesives. Electrical connections are performed by the insertion of metallic micro-tips in a ductile material. As a low-temperature process and fluxless technology, this method is adapted to fine-pitch and large devices. As a proof of concept, we present the bonding results obtained on fine-pitch large arrays of daisy chains with 500 times 500 contacts and 30 -mum pitch. The electrical contact has been demonstrated and characterized in terms of resistance and yield.

A 10μm pitch interconnection technology using micro tube insertion into Al-Cu for 3D applications

Future 3-D applications require a very low pitch for inter-strata vertical interconnection. The last International Technology Roadmap for Semiconductors (ITRS) assessment for vertical interconnection predicts a need for decreasing the interconnection pitch to 10μm [1]. The room-temperature insertion technology has been proposed and developed using micro tubes as inserts [3] to address many assembling difficulties of industrial process. In the present work, we study the mechanical and electrical behavior of a single micro tube insertion into Al-0.5Cu pads. A modified nanoindenter with a very accurate load and displacement control is used, coupled with an electrical measurement device to qualify the insertion process. Finally, the best Die To Wafer (D2W) parameters are determined thanks to a composed experimental design.

Micro tube insertion into indium, copper and other materials for 3D applications

The viability of inter-strata low pitch vertical interconnection technologies is mandatory for 3D applications. In order to increase the connection complexity and to reach a 10μm or even smaller interconnection pitch, a new room-temperature insertion technology has been proposed and developed using micro tubes as inserts [1]. In the present work, we study the load required to obtain a full and efficient insertion of a single micro tube into indium, copper or other materials. We use a modified nanoindenter with a very accurate load and displacement control, to qualify the insertion process. The nature of the couple constituted by the insert and the soft metal is of major importance. Our study focuses on two specific parameters: Mechanical properties of the soft metal; Combined geometries of the soft metal and the insert. Thanks to this study, we can give the best conditions to improve insertion load and time for different couple. Finally, some first chips hybridizations are performed and tested mechanically and electrically to validate our work.

Aluminum to Aluminum bonding at room temperature

In this work we show that high density and very low pitches face to face Aluminum/Aluminum cold bonding is feasible when using Aluminum coated micro-tubes inserted into Aluminum pads. First, mechanical simulations by FEM show that the insertion pressure felt on the top edge of the Aluminum coated micro-tube is sufficient to break native aluminum oxide present at the interface and also insure the large plastic deformation of aluminum terminations necessary for good electrical and mechanical contact at the joint. Then an electrical demonstrator with over 106 connections at a 10 μm pitch is designed, assembled and characterized: the resistance values of the Al/Al bonds prove to be similar to those obtained with Au/Al bonds. Ion Beam cross-sections associated with SEM microscopy is used to characterize the morphology of the interface and shows that seamless Al/Al interfaces can be obtained if certain conditions are fulfilled. Finally the fundamentals of the cold insertion bonding process are discussed and a relationship established with “cold roll bonding” mechanisms, it is shown that the two techniques present some similarities related to very large plastic deformations of bonded materials. This helps us to develop a bonding theory to thoroughly explain the mechanism of the Aluminum/Aluminum bonds formation during the insertion process, as well as its kinematic scenario.

Integration of advanced optical functions on the focal plane array for very compact MCT-based micro cameras

Over the past decade, several technological breakthroughs have been achieved in the field of optical detection, in terms of spatial and thermal resolutions. The actual trend leads to the integration of new functions at the vicinity of the detector. This paper presents two types of integrated optics in the cryo-cooler, close to the MCT (CdHgTe) infrared detector array. The first one, for spectro-imaging applications, is a Fourier-transform microspectrometer on chip (MICROSPOC), developed for very fast acquisition of spectral signatures. Experimental results will be presented. The second one, for large field of view applications, illustrates the high potentiality of the integration of advanced optical functions in the Dewar of MCT detectors.

Technological and Electrical Performances of Ultrafine-Pitch Flip-Chip Assembly Based on Room-Temperature Vertical Interconnection

Flip-chip is a high-density and highly reliable interconnection technology, which is widely used for the fabrication of infrared complementary metal-oxide-semiconductor imagers. In order to increase the format and the resolution of staring arrays to 2000 × 2000 pixels or even larger complexities, while keeping substrate dimensions and device cost low, there is a general trend in reducing pixel size. But this results in a very challenging process control for ultrafine-pitch and high-count flip-chip bonding technology. A new room-temperature insertion technology has been proposed and developed to alleviate most of these issues. It overcomes the planarity and thermal mismatch issues of this heterogeneous assembly made of cadmium mercury telluride detectors hybridized on silicon read-out circuits while reducing the bonding thermocompression forces and the hybridization temperature. The technological preparation of the assembled devices is described in this paper. A process characterization, using a modified nanoindenter with instrumentation for single tip insertion, has been achieved to evaluate insertion mechanical parameters. This paper gives also the first measured interconnection yield and vertical access resistance of 2000 × 2000 hybridized arrays of 10 μm pitch, fabricated using the proposed insertion flip-chip technique. Connection results are discussed, and a comparative study proves that parallelism during insertion is a key parameter. When providing a perfect parallelism control with advanced new flip-chip bonders, the microtip insertion technique is scalable to complexities of over 4 million connections at very fine pitch. Moreover, this new low-temperature insertion concept could possibly be applied to 3-D interstrata interconnections for electronic devices. Indeed, it avoids the issues caused by cumulative high-temperature cycles, which are typical of more conventional processes.

Indium deposition processes for ultra fine pitch 3D interconnections

With the miniaturization and the new capabilities in CMOS process, the interconnection pitch between a die and its circuits must be reduced as well. Therefore not only must the assembly steps adjust to the criterion associated with smaller pitches but the back-end wafer processing as well [1]. In this paper we present two fabrication processes for the bumping of 8” wafers with pitches as low as 15µm. Indium was used as the solder and an electroplated deposition method as well as an evaporation method were developed. The two were qualified in term of bump height uniformity, process easiness, and were finally compared. A uniformity below 2% was obtained for the evaporation method and assemblies of large pixels array at a 15µm pitches achieved 99.9% to 100% connections. For the electroplating process uniformity of about 2–3% on the die and 7% on the wafer was achieved but no assemblies were performed.

Surface shaping and 3D integration of optical functions on photo detector, using an optimized reflow process of solder Bumps

Solder bumps are widely used in micro electronic devices, for electrical interconnection. The solder bumps diameter can range, from 15μm, for detector with fine pixel pitch [1] to several millimeters for BGA (Ball Grid Array) packaging. For electrical interconnection, most important parameters of solder bumps are to have low resistance and efficient contact for all connection. However, solder bumps can be used to bring other functions to electronic assemblies. This paper presents the added value of solder bumps parameter (predictable shape, reflow temperature) coupling with self alignment for device positioning. The study focuses on low temperature solder bumps materials like indium or InSn alloy and the solder shape after reflow. Taking into account these parameters, it is possible to control the solder bump interconnection to add functions to microelectronic components and therefore bring more value to them (especially for optical and MEMS-based systems). Also, such a technique is compatible with low cost manufacturing and high volume production, since it can be implemented at wafer level. Two specific applications will be presented on this paper. The first application is about surface shaping and the second application is about 3D stack assembly for height passive control.

Thermomechanical characterization of electronic components

The main objective of this study is to validate the thermomechanical properties of materials used in some electronic components. The improved performance of HgCdTe infrared focal plane arrays requires reliability of the assembly at low temperatures down to 77K. Unfortunately, the thermomechanical behavior of most materials of these components remains to be clarified, particularly in a cryogenic environment. The present investigation is a part of a global study that aims to analyze the reliability of some electronic assembly, through numerical simulations combined with experimental measures. The relevance of this numerical modelling strongly depends on a precise characterization of the thermo-mechanical behavior of specific materials involved in the considered assemblies. Thus, through numerical simulations of a model of electronic chip, we determine the thermal and mechanical properties of materials such as indium, silicon, fused silica, by comparing these simulations results with the experimental measurements carried out on these same models of chips. This study enables us to have a complete database of the thermomechanical behavior of materials studied for the range of operating temperatures.