H.S. Kang

Optimization of safe-operating-area using two peaks of body-current in submicron LDMOS transistors

The analysis of hot-electron-limited SOA (Safe-Operating-Area) and electrical SOA using two peaks of body current in 20 V LDMOS transistors was investigated for the first time. The origin of the two peaks can be explained in terms of hot carrier injection phenomena. The first peak shows the appearance of weak impact ionization related to the device degradation and the second peak shows the occurrence of the snap-back phenomenon predicting device destruction, respectively.

The new high voltage level up shifter for HVIC

A new high voltage level up shifter for high-voltage integrated circuits (HVIC) is presented that combines the optimized shape of a high doping concentration layer (N+ buried layer) and low doping isolation. In order to realize the high voltage level up shifter for HVIC, not only the P-doping level for isolation area but also the shape of N+ buried layer is very important. In P-doping level, it is hard to find the optimized condition. If the doping level is higher than proper condition, the breakdown voltage is lower than 600 V. In the opposite case, there is leakage currents between active to active area. After several experiments, one can find the optimized condition for P- isolation-around 8E12 ion/cm/sup 2/. Under the optimized Pisolation condition, the shape of the N+ buried layer decides the breakdown voltage of the level up shifter. According to experimental result, as the edge radius of the N+ buried layer increases from 0 /spl mu/m to 100 /spl mu/m, the breakdown voltage of the level up shifter increases from 355 V to 645 V under the same vertical structure and process conditions.

A 650 V rated RESURF-type LDMOS employing an internal clamping diode for induced bulk breakdown without EPI layer

A new LDMOS employing an internal clamping diode is proposed in order to prevent surface breakdown which is a weak point of RESURF Type LDMOS. The clamping diode of N+/N-/P-well/P-sub was fabricated by cutting n-well located below drain contact and inserting p-well. Breakdown stabilization was realized by inducing bulk breakdown at the clamping diode without the increase of Ron,sp (specific on resistance) when width of p-well was designed to 12 um.

Newly designed isolated RESURF LDMOS transistor for 60 V BCD process provides 20 V vertical NPN transistor

RESURF LDMOS transistors are utilized in high side driver applications and other applications that mandate electrical isolation between source and substrate by using isolated RESURF technology. However, the BCD process using conventional isolated RESURF LDMOS structures cannot provide high efficiency vertical NPN transistors due to the dependence of the RESURF LDMOS BV/sub dss/ (source to drain breakdown voltage) upon the epi thickness. In this paper, we propose a new isolated RESURF LDMOS. With the use of n-well near the drain region, we can avoid electric field concentration below the drain region. P-well dose, p-well length and extended drain dose should be optimized to reduce surface field of the proposed isolated RESURF LDMOS regardless of epi thickness.

A high performance complementary bipolar process using PBSOI technique

In this paper, for the first time, we suggest a novel high voltage, high speed and latch-up free NPN transistor and PNP transistor fabrication technology using PBSOI (Patterned and Bonded Silicon On Insulator) and STI (Shallow Trench Isolation) technology. Using this technique, we can easily control the breakdown voltage (BVceo) without the problem of P+B/L out-diffusion. In this PBSOI process, after diffusion of well (collector), the Buried Layer is diffused on the well. In addition, unlike the prior technology that devices are fabricated in epitaxial layer, the proposed devices are formed in active wafer itself, therefore we can get defect-free devices promising excellent characteristics. The peak fTs for NPN and PNP transistor are 10 GHz and 9 GHz, the values of BVceo for the NPN and PNP devices are 15 V and 17 V, respectively. Finally, these values were found to be excellent results as shown in the maximum value of Johnson-limit for the fT-BVceo product.

A low on resistance 700V charge balanced LDMOS with intersected WELL structure

A new 700V rate charge balanced LDMOS structure is proposed. The key feature of this structure is the intersected N-Well and P-Well that divides drift region into multi parallel conduction path. Ron,sp can be reduced by considerably high doped N-Well region and surface electric field can be dispersed by each Well junction. Ron,sp of the proposed LDMOS is reduced by 55% compared with conventional LDMOS. This value nearly gets to the limit of LDMOS made by bulk silicon. The surface electric field that can cause fatal failure of LDMOS in reliability characteristics is decreased by 30% compared with conventional LDMOS. The position occurring breakdown was moved from surface to bulk below drain contact in the proposed LDMOS.A new 700V rate charge balanced LDMOS structure is proposed. The key feature of this structure is the intersected N-Well and P-Well that divides drift region into multi parallel conduction path. Ron,sp can be reduced by considerably high doped N-Well region and surface electric field can be dispersed by each Well junction. Ron,sp of the proposed LDMOS is reduced by 55% compared with conventional LDMOS. This value nearly gets to the limit of LDMOS made by bulk silicon. The surface electric field that can cause fatal failure of LDMOS in reliability characteristics is decreased by 30% compared with conventional LDMOS. The position occurring breakdown was moved from surface to bulk below drain contact in the proposed LDMOS.

Extension of safe-operating-area by optimizing body-current in submicron LDMOS transistors

We present the extension of Hot-Electron-Limited SOA and Electrical SOA by optimising the two peaks of body current in 20 V LDMOS Transistors. The LDMOS has two peaks of body current and the origin of two peaks can be explained through hot carrier injection phenomenon. The first peak shows the appearance of weakly impact ionization related to the device degradation and the second peak shows the occurrence of snap-back phenomenon predicting device destruction, respectively.

Design parameter optimization for Hall sensor application

A Hall effect sensor using a 7 /spl mu/m, 1.7 /spl Omega/-cm bipolar process was successfully developed. The Hall sensor consists of various patterns, such as regular shapes, rectangles, diamond, hexagon and cross shapes, to optimize offset voltage and sensitivity for proper applications. In order to measure offset voltage at chip scale, the Agilent 4156C and nano-voltage meter were used and the best structure in offset voltage terms was finally selected by using a ceramic package. The patterns appear to be quadri-rectangular patterns entirely and three-parallelogram patterns. The measured offset voltages were found to be about 173/spl sim/365 /spl mu/V. Meanwhile, in the offset voltage, the standard deviation of the measured values is more important than the average value itself because the unfavorable offset voltages due to mainly misalignment between PISO and N+CONT can be easily overcome by the Hall IC fabrication with compensated processing circuitry. The standard deviation ranges from 78 to 188. The measured misalignment is about 0.32 /spl mu/m. After measuring the offset voltages, we checked the sensitivity by using the Lakeshore electromagnetic field measurement tool. We selected the best patterns for the sensitivity. The measured sensitivities are about 11/spl sim/18 mV/gauss. Furthermore, thermal drift was measured with increasing temperature and the values showed linearity ranging from 0 /spl deg/C to 120 /spl deg/C.

Submicron BCDMOS process with extended LDMOS safe-operating-area by optimizing body current

A 20V submicron BCDMOS process is presented with extended LDMOS SOA (Safe-Operating-Area) for smart power applications by optimizing body-current. The LDMOS has two peaks of body current and the origin of two peaks can be explained through hot carrier injection phenomenon. The first peak shows the appearance of weakly impact ionization related to the device degradation and the second peak shows the occurrence of snap-back phenomenon predicting device destruction, respectively. In the present paper, we investigated the HE-SOA (Hot-Electron-Limited SOA) and Electrical SOA using two peaks of body current in LDMOS transistors with submicron BCD process.

Self-aligned extended-drain with compensating ion-implantation for extended-SOA in 30 V lateral MOS

A compensating ion-implantation method is introduced to make self-aligned extended-drain of 30 V lateral NMOS and PMOS transistors with the only one mask and to help the improvement of electrical SOA through the shift of the critical electric field position. In general, high voltage lateral MOS has been useful for high current and high voltage applications. In that case, we have to check up the critical electric field position and the current flow line occurring hot-carrier injection phenomenon because it results in unfavorable device destruction by secondary breakdown. In this paper, we shifted the critical electric field position from n+ drain edge to n+ drain bottom using self-aligned extended-drain formed by compensating ion-implantation. As a result, the occurrence of the secondary breakdown due to Kirk effect would be postponed.