Chung-woo Kim

Large capacitance-voltage hysteresis loops in SiO2 films containing Ge nanocrystals produced by ion implantation and annealing

This work was partially supported by the QuantumFunctional Semiconductor Research Center in Dongguk University and by the National Program for Tera Level Nano Devices through MOST. S.-H.C. acknowledges partial support from the National Research Program for the 0.1 Terabit Non-Volatile Memory Development sponsored by Korea Ministry of Science & Technology. R.G.E. additionally acknowledges the Australian Research Council for their partial financial support of this work.

Highly thermally stable TiN nanocrystals as charge trapping sites for nonvolatile memory device applications

TiN nanocrystals formed by a co-sputtering method have been investigated as discrete charge traps for metal–oxide–nitride–oxide–silicon-type nonvolatile memory devices. The formation of isolated TiN nanocrystals embedded in Al2O3 was confirmed by transmission electron microscopy, x-ray photoelectron spectroscopy, and x-ray diffraction analyses. In addition, superior thermal stability of TiN nanocystals embedded in Al2O3 was confirmed. Compared to the control samples without TiN nanocrystals, Al2O3 layers with TiN nanocrystals exhibited wider capacitance–voltage hysteresis and this in turn showed better charge trapping characteristics due to the incorporation of TiN nanocrystals into Al2O3.

Memory characteristics of silicon nitride with silicon nanocrystals as a charge trapping layer of nonvolatile memory devices

Silicon nitride with silicon nanocrystals formed by low-energy silicon plasma immersion ion implantation has been investigated as a charge trapping layer of a polycrystalline silicon-oxide-nitride-oxide-silicon-type nonvolatile memory device. Compared with the control sample without silicon nanocrystals, silicon nitride with silicon nanocrystals provides excellent memory characteristics, such as larger width of capacitance-voltage hysteresis, higher program∕erase speed, and lower charge loss rate at elevated temperature. These improved memory characteristics are derived by incorporation of silicon nanocrystals into the charge trapping layer as additional accessible charge traps with a deeper effective trap energy level.

Interface-modified random circuit breaker network model applicable to both bipolar and unipolar resistance switching

We observed reversible-type changes between bipolar (BRS) and unipolar resistance switching (URS) in one Pt/SrTiOx/Pt capacitor. To explain both BRS and URS in a unified scheme, we introduce the “interface-modified random circuit breaker network model,” in which the bulk medium is represented by a percolating network of circuit breakers. To consider interface effects in BRS, we introduce circuit breakers to investigate resistance states near the interface. This percolation model explains the reversible-type changes in terms of connectivity changes in the circuit breakers and provides insights into many experimental observations of BRS which are under debate by earlier theoretical models.

High work-function metal gate and high-/spl kappa/ dielectrics for charge trap flash memory device applications

We report the impact of high work-function (/spl Phi//sub M/) metal gate and high-/spl kappa/ dielectrics on memory properties of NAND-type charge trap Flash (CTF) memory devices. In this paper, theoretical and experimental studies show that high /spl Phi//sub M/ gate and high permittivity (high-/spl kappa/) dielectrics play a key role in eliminating electron back tunneling though the blocking dielectric during the erase operation. Techniques to improve erase efficiency of CTF memory devices with a fixed metal gate by employing various chemicals and structures are introduced and those mechanisms are discussed. Though process optimization of high /spl Phi//sub M/ gate and high-/spl kappa/ materials, enhanced CTF device characteristics such as high speed, large memory window, and good reliability characteristics of the CTF devices are obtained.

Conversion from unipolar to bipolar resistance switching by inserting Ta2O5 layer in Pt/TaOx/Pt cells

We observed unipolar resistance switching in Pt/TaOx/Pt cells. We could make the cell have the bipolar resistance switching by inserting a stoichiometric Ta2O5 layer between Pt and TaOx layers. Bipolar resistance switching in Pt/Ta2O5/TaOx/Pt cells occurred reliably without applying an external compliance current. With increase in the Ta2O5 layer thickness, the current value at the low-resistance state became decreased but the forming voltage became increased. We could explain these intriguing phenomena using the interface-modified random circuit breaker network model.

Impact of metal work function on memory properties of charge-trap flash memory devices using fowler-nordheim P/E mode

This letter reports the impact of metal work function (/spl Phi//sub M/) on memory properties of charge-trap-Flash memory devices using Fowler-Nordheim program/erase mode. For eliminating electron back tunneling and hole back tunneling through the blocking oxide during an program/erase operation, a gate with /spl Phi//sub M/ of 5.1-5.7 eV on an Al/sub 2/O/sub 3/-SiN-SiO/sub 2/ (ANO) stack is necessary. Compared to a thickness optimized n/sup +/ poly-Si/ONO stack, a high-work-function gate on an ANO stack shows dramatic improvements in retention versus minimum erase state.

Reduction in high reset currents in unipolar resistance switching Pt/SrTiOx/Pt capacitors using acceptor doping

The high reset current, IR, in unipolar resistance switching is an important issue which should be resolved for practical applications in nonvolatile memories. We showed that, during the forming and set processes, the compliance current, Icomp, can work as a crucial parameter to reduce IR. Doping with Co or Mn can significantly reduce the leakage current in capacitors made using SrTiOx film, opening a larger operation window for Icomp. By decreasing Icomp with acceptor doping, we could reduce IR in SrTiOx films by a factor of approximately 20. Our work suggests that the decrease in Icomp by carrier doping could be a viable alternative for reducing IR in unipolar resistance switching.

Time-dependent current-voltage curves during the forming process in unipolar resistance switching

We investigated the time-dependent current-voltage curves of the forming process in unipolar resistance switching. We applied triggered-voltage triangular-waveform (pulse-waveform) signals with varied sweep rate (amplitude) to Pt/SrTiOx/Pt capacitors. By investigating their temperature dependences, we found that the forming process was driven by two different mechanisms, depending on the sweep rate (amplitude): a purely electrical dielectric breakdown and a thermally assisted dielectric breakdown. For the latter process, we observed precursory changes in the current I(t) before the forming process. By fitting the time-dependent precursory changes with I(t)=Io−A exp(−t/τ), we suggest that the thermally activated migration of oxygen vacancies/ions could help the thermally assisted dielectric breakdown.

Annealing temperature dependence of capacitance-voltage characteristics in Ge-nanocrystal-based nonvolatile memory structures

The annealing temperature (TA) dependence of capacitance-voltage (C-V) characteristics has been studied in metal-oxide-semiconductor structures containing Ge nanocrystals (NCs) produced by ion implantation and annealing. These structures are of interest for application as nonvolatile memory and TA is shown to have a strong influence on the C-V hysteresis. This behavior is shown to be correlated with structural changes of the Ge NCs which have been characterized by synchrotron-radiation photoemission spectroscopy. Specifically, well-defined C-V characteristics with large hysteresis were found only for annealing temperatures greater than 950 °C where Ge nanocrystals are known to form. In this temperature regime, transmission electron microcopy and energy dispersive x-ray spectroscopy demonstrate the existence of regularly arranged Ge NCs of approximately 3–5 nm diameter located around 6.7 nm from the interface.