H. Terai

A single flux quantum standard logic cell library

To expand designable circuit scale, we have developed a new cell-based circuit design for single flux quantum (SFQ) circuit. We call it CONNECT cell library. The CONNECT cell library has over 100 cells at present. Each CONNECT cell consists of a Verilog digital behavior model, circuit information, and a physical layout. All circuit parameter values have been optimized for obtaining the widest margins and minimizing interactions between cells. At the layout level, we have defined a minimum standard cell size and made cell height and width a multiple of the size. Using this cell library, we can easily expand circuit scale without the time-consuming dynamic simulations of whole circuits. For estimation of the reliability of the library, we designed and fabricated test circuits using CONNECT cells. We demonstrated experimentally correct operations, which means the CONNECT cell library is sufficiently reliable.

On-chip test of the shift register for high-end network switch based on cell-based design

We have demonstrated the high-speed operation up to 55 GHz with a bias margin of ±5.5% for a shift register based on the single-flux-quantum logic circuit. The shift register is employed in the rate transfer circuit in high-end network switches that are made up with the cell-based design technique. The on-chip test system was used for measuring the operation frequencies, and the test system itself was built by combining the cells to satisfy the boundary conditions between the test system and the circuit-under-test. As a result, the on-chip test system developed in this study has high flexibility.

Design and implementation of circuit components of the SFQ microprocessor, CORE1

We have designed, implemented and tested several circuit components of a prototype of the SFQ microprocessor, CORE1. CORE1 is a synchronously clocked 8 bit microprocessor based on a bit-serial architecture. We have designed its circuit components using a cell-based design approach and an automated top-down CAD environment. We have successfully obtained correct operations of all circuit components, including an instruction register, a program counter and a controller.

Measurement of crosstalk between crossing superconductor microstrip lines

Abstract We experimentally evaluated the effect of crosstalk between crossing microstrip lines (MSLs) on our MSL receiver. The measurement circuit consisted of two crossing MSLs, referred to as the upper MSL and lower MSL. At the crossing area, the upper MSL and lower MSL were separated by a 400-nm thickness of SiO 2 thin film. The parasitic capacitance between them was estimated to be about 0.1 pF. We measured bias margin of the receiver connected to the lower MSL under two conditions: with a pulse train running through the upper MSL, i.e., with crosstalk noise, and without a pulse train in the upper MSL, i.e., without crosstalk noise. Our measurements showed that (i) crosstalk mainly reduced the lower limit of the receiver’s bias margin, and (ii) this reduction of bias margin was enhanced by resonance when the repetition frequency of pulses in the upper ring satisfied resonance condition.

Advanced design approaches for SFQ logic circuits based on the binary decision diagram

We have been investigating a design methodology of SFQ logic circuits based on the binary decision diagram (BDD). In the previously proposed BDD SFQ logic circuits, we have used one-to-two binary switches as a node cell in a BDD tree. In this study we will propose a new implementation method of SFQ BDD circuits, in which two nodes are implemented by using a 2-input 2-output switch gate. By employing the new approach, we have designed and implemented a one-bit full adder using the NEC 2.5 kA/cm/sup 2/ Nb standard process and the CONNECT cell library. The maximum operating frequency of the full adder was found to be 40 GHz by circuit simulations and 32.8 GHz by on-chip high-speed tests.

Component test toward single-flux-quantum processors

Abstract We have developed essential components for most of microarchitectures based on the single-flux-quantum (SFQ) logic. The circuit under test is composed of two registers, an ALU and a control unit, and made up of about 540 cells, 1600 Josephson junctions on 1.5xa0×xa02.4 mm area. We have obtained the correct results by a sequence of several instructions, in which two integers are written into the registers with the LOAD and COPY operations, and then execute the ADD operation. Some of their functions were tested at both low and high frequencies. As a result, we found that the designed components could work at 15 GHz for the designed bias current and up to 18 GHz for higher bias currents.

Transport properties of YBCO/PBCO/YBCO junctions

We studied on the transport properties of edge-type YBCO/PBCO/YBCO junctions. They showed clear Josephson characteristics with I/sub c/R/sub n/ products of a few mV. The experimental results revealed that normal-state characteristics were dominated by the tunneling via localized states. Besides, taking account of constant I/sub c/R/sub n/ products, we could consider the transport mechanism of supercurrent as the resonant tunneling.<<ETX>>

Electrical interface structure in YBa/sub 2/Cu/sub 3/O/sub 7-x//metal contact

We have investigated the electrical contacts between YBa/sub 2/Cu/sub 3/O/sub 7-x/ (YBCO) and Au. The dI/dV characteristics of the c-axis-oriented YBCO/Au/Nb junctions reveal the existence of a tunnel barrier at the YBCO/Au interface. The experimental results of the YBCO/LaGaO/sub 3//Au/Nb junction suggest p-type degenerate semiconductor-like behavior of YBCO along the c-axis direction. The anomalously small I/sub c/R/sub n/ of a few /spl mu/V in the c-axis direction are interpreted as the band bending at the YBCO surface. On the other hand, the experimental I/sub c/R/sub n/ value of 120 /spl mu/V in the a-axis-oriented YBCO/Au/Nb junction is understood within the scope of conventional theory.<<ETX>>

Design and high-speed test of (4 × 8)-bit single-flux-quantum shift register files

In the realization of large-scale single-flux-quantum (SFQ) digital systems, one of the most serious problems is the lack of high-density and high-speed memories. We have been developing random access memories using SFQ shift registers, which are one candidate to solve the memory problem in the SFQ digital system because of their high throughput and short access time. In this paper we have designed and tested a (4 × 8)-bit SFQ shift register file as a demonstration of the SFQ shift register memory system. Its target clock frequency is 20 GHz assuming an NEC 2.5 kA cm−2 Nb standard process. In the test, we have confirmed that 8-bit dual-rail data can be loaded to appropriate shift registers specified by 2-bit address data. We have also verified that the loaded data are read out and written back to the same shift register at high speed. A tested dc bias margin at 20 GHz is ±5%.

The influence of the ground current on large-scale single-flux-quantum circuits

In this study we have investigated the influence of an externally applied ground current on large-scale single-flux-quantum (SFQ) circuits. A Josephson transmission line containing 104 junctions with a total bias current of 1.8 A was examined for this purpose. The test results show that the ground current affects the circuit operation remarkably strongly. In the worst case, the ground current of about 10xa0mA for a 5xa0mm die chip disturbs the circuit operation. The results also show that DC/SFQ and SFQ/DC converters are very sensitive to the ground current. To eliminate the effect of the ground current, we have made SFQ circuits completely shielded from the external magnetic field by using upper and lower ground planes. It was found that the shielded SFQ circuits are much less sensitive to the ground current. These results show that the magnetic shielding structure is one solution for reducing the effects of the ground current and hence the external magnetic field.