Yoshio Kameda

A single flux quantum standard logic cell library

To expand designable circuit scale, we have developed a new cell-based circuit design for single flux quantum (SFQ) circuit. We call it CONNECT cell library. The CONNECT cell library has over 100 cells at present. Each CONNECT cell consists of a Verilog digital behavior model, circuit information, and a physical layout. All circuit parameter values have been optimized for obtaining the widest margins and minimizing interactions between cells. At the layout level, we have defined a minimum standard cell size and made cell height and width a multiple of the size. Using this cell library, we can easily expand circuit scale without the time-consuming dynamic simulations of whole circuits. For estimation of the reliability of the library, we designed and fabricated test circuits using CONNECT cells. We demonstrated experimentally correct operations, which means the CONNECT cell library is sufficiently reliable.

The effects of DC bias current in large-scale SFQ circuits

The supply of bias current is one of the key problems to be overcome for fully operational large-scale SFQ circuits. Large currents cause various undesirable effects that degrade circuit operation. The magnetic field induced by a large DC bias current affects the operation of several SFQ cells, even with a microstrip-line structure applied for the bias lines. In this paper, experimental results using SQUIDs show that bias-line shielding is the most effective way to reduce the effect of the DC bias current. The operating margins of SFQ cells were also found to be sensitive to the current in the ground plane. The location of a ground bonding should be close to the point of current injection if we wish to avoid undesirable diffusion of current through the ground plane. We confirmed the effectiveness of bias-line shielding and of the location of ground bonding with a circuit composed of about 500 junctions.

A design approach to passive interconnects for single flux quantum logic circuits

We developed a design approach for interface circuits to connect Single Flux Quantum (SFQ) cells by using passive transmission lines (PTLs). In the approach, an interface circuit between a PTL and JTL is optimized to obtain a standard interface circuit, and then, modifications are made to previously designed SFQ cells and the standard interface circuit to connect the SFQ cells by using PTLs. The key point is the use of approximately the same interface circuit with every SFQ cell to maintain the matching condition between the interface circuit and the PTLs. Based on this approach, we designed an interface circuit and a test circuit composed of two D-flip-flops connected using 2-mm-long PTLs via the interface circuits. The impedance of the PTL was 2 /spl Omega/. We achieved high-speed operation of the test circuit up to 35 GHz with a bias margin of -15/+30%.

Low-cost gate-oxide early-life failure detection in robust systems

We present a new low-cost technique for detecting gate-oxide early-life failures (ELF) to overcome reliability challenges in robust systems without requiring expensive concurrent error detection. Our approach is enabled by an on-chip clock control technique, applied during periodic on-line self-test and diagnostics, to detect delay shifts over time before functional failures occur. Using 90nm test chips, we demonstrate the following key results: 1. A gate-oxide ELF transistor inside a combinational logic circuit results in delay shifts over time before functional failures appear. 2. The delay shifts can be successfully detected during on-line self-test and diagnostics using our on-chip clock control technique.

Implementation of a 4 /spl times/ 4 switch with passive interconnects

We designed and fabricated a 4 /spl times/ 4 switch in which all interconnections were implemented using passive transmission lines (PTLs). The switch consisted of four identical 2 /spl times/ 2 switches connected using PTLs. The 2 /spl times/ 2 switch was designed using gate-to-gate passive interconnections. Using the on-chip testing method, we demonstrated 40-GHz operation of the 4 /spl times/ 4 switch. To verify the effectiveness of passive interconnection, we compared the 4 /spl times/ 4 switch with an identical switch that was designed using Josephson transmission lines (JTLs) for interconnections. The comparison showed that the PTL-version 4 /spl times/ 4 switch had 50% fewer junctions and required 55% less powering current. The latency and the largest jitter in the PTL-version 4 /spl times/ 4 switch were estimated to be 36% and 61%, respectively, of those of the JTL version.

On-chip test of the shift register for high-end network switch based on cell-based design

We have demonstrated the high-speed operation up to 55 GHz with a bias margin of ±5.5% for a shift register based on the single-flux-quantum logic circuit. The shift register is employed in the rate transfer circuit in high-end network switches that are made up with the cell-based design technique. The on-chip test system was used for measuring the operation frequencies, and the test system itself was built by combining the cells to satisfy the boundary conditions between the test system and the circuit-under-test. As a result, the on-chip test system developed in this study has high flexibility.

Implementation and Experimental Evaluation of a Cryocooled System Prototype for High-Throughput SFQ Digital Applications

We report on development of a cryocooled system prototype for high-throughput single flux quantum (SFQ) digital applications. The system was designed to have 32 I/O links with a bandwidth of 10 Gbps/port. An SFQ multi-chip module (MCM), double mu-metal magnetic shields, a 40-K radiation shield, customized GaAs cryogenic amplifiers, a 32-pin wide-bandwidth cryo-probe, and 32 I/O cables were packaged in a vacuum chamber together with a two-stage 4-K 1-W Gifford-McMahon (G-M) cryocooler. S-parameter measurements showed that the analog bandwidth of the I/O link was 23 GHz. We demonstrated high-speed cryocooled operation of a test module, in which a 5 mm times 5 mm SFQ circuit chip was flip-chip bonded on a 16 mm times 16 mm MCM carrier with phi30 mum InSn bump bonds, at bit rates up to 12.5 Gbps. Measured bit error rate (BER) was less than 10-12 for a 1023 - 1 pseudorandom bit sequence (PRBS) at 10 Gbps.

Experimental study of gate oxide early-life failures

Large-scale experimental data from 90nm test chips consisting of 49,152 transistors, and experiments on 90nm test chips containing inverter chains are used to establish: 1. A gate-oxide early-life failure (ELF, also called infant mortality) candidate transistor produces gradually degraded drive currents over time; 2. A digital circuit path consisting of a gate-oxide ELF candidate transistor experiences gradual delay shifts over time before the circuit produces functional failures. These results may be utilized to effectively overcome ELF challenges in scaled CMOS technologies.

Development of Cryopackaging and I/O Technologies for High-Speed Superconductive Digital Systems

A cryocooled system with I/O interface circuits, which enables high-speed system operation of superconductive single-flux-quantum (SFQ) circuits at over 40GHz, and the demonstration of a 47-Gbps SFQ 2×2 switch system are presented. The cryocooled system has 32 I/Os and cools an SFQ multi-chip module (MCM) to 4K with a two-stage 1W Gifford-McMahon cryocooler. An SFQ 4:1 multiplexer (MUX) and an SFQ 1:4 demultiplexer (DEMUX) have been designed to interface the speed gap between the I/O (-10Gbps/ch) and SFQ circuits (>40GHz). An SFQ 2×2 switch chip, in which the MUX/DEMUX and an SFQ 2×2 switch are integrated, and an 8-channel superconductive voltage driver (SVD) chip have been designed with an advanced cell library for a junction critical current density of 10kA/cm2. An SFQ 2×2 switch MCM has been made by flip-chip bonding the switch chip and SVD chip on a superconductive MCM carrier with ∅50-μm InSn solder bumps. An SFQ 2×2 switch system, which is the switch MCM packaged in the cryocooled system, has been demonstrated up to a port speed of 47Gbps for the first time.

Superconducting digital electronics

Superconducting devices have intrinsically superior characteristics to those of semiconductor devices. Presently, we can fabricate more than twenty thousand junctions on one chip using niobium technology. We have demonstrated the operation of a network system with a superconducting interconnection chip using voltage-state logic. Single flux quantum devices are promising for future superconducting applications because the clock frequency of SFQ logic is higher than that of voltage-state. We have proposed a high-end switch based on hybrid architecture using optical devices, semiconductors and SFQ devices. To demonstrate the high-speed operation of SFQ circuits, we developed an arbiter circuit that uses SFQ components and the arbiter circuit operates at 60 GHz. We also have developed a high Tc superconducting (HTS) SFQ sampler system for observing ultra-fast signal waveforms. In addition, we will discuss the prospects of future superconducting devices based on the fabrication technologies we developed.