Hadi Heidari
University of Glasgow
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Publication
Featured researches published by Hadi Heidari.
Advanced Robotics | 2015
Nivasan Yogeswaran; Wenting Dang; William Taube Navaraj; Dhayalan Shakthivel; Saleem Khan; Emre O. Polat; Shoubhik Gupta; Hadi Heidari; Mohsen Kaboli; Leandro Lorenzelli; Gordon Cheng; Ravinder Dahiya
Flexible electronics has huge potential to bring revolution in robotics and prosthetics as well as to bring about the next big evolution in electronics industry. In robotics and related applications, it is expected to revolutionise the way with which machines interact with humans, real-world objects and the environment. For example, the conformable electronic or tactile skin on robot’s body, enabled by advances in flexible electronics, will allow safe robotic interaction during physical contact of robot with various objects. Developing a conformable, bendable and stretchable electronic system requires distributing electronics over large non-planar surfaces and movable components. The current research focus in this direction is marked by the use of novel materials or by the smart engineering of the traditional materials to develop new sensors, electronics on substrates that can be wrapped around curved surfaces. Attempts are being made to achieve flexibility/stretchability in e-skin while retaining a reliable operation. This review provides insight into various materials that have been used in the development of flexible electronics primarily for e-skin applications.
IEEE Transactions on Circuits and Systems | 2015
Hadi Heidari; Edoardo Bonizzoni; Umberto Gatti; Franco Maloberti
A Hall magnetic sensor working in the current domain and its electronic interface are presented. The paper describes the physical sensor design and implementation in a standard CMOS technology, the transistor level design of its high sensitive front-end together with the sensor experimental characterization. The current-mode Hall sensor and the analog readout circuit have been fabricated using a 0.18- μm CMOS technology. The sensor uses the current spinning technique to compensate for the offset and provides a differential current as an output signal. The measured sensor power consumption and residual offset are 120 μW and 50 μT, respectively.
IEEE Sensors Journal | 2016
Hadi Heidari; Edoardo Bonizzoni; Umberto Gatti; Franco Maloberti; Ravinder Dahiya
This paper presents the realization of different vertical Hall sensors (VHSs) implemented using a 0.18-μm CMOS technology and mounted on flexible substrates. Various geometries of VHS have been studied to obtain the optimum sensor device dimension and shape. COMSOL multiphysics simulation results are validated with respect to the electrical behaviour of an eight-resistor Verilog-A model implemented in Cadence environment. Simulation and measurement results are in good agreement. The use of polymeric foils and current spinning technique compensate for the effects caused by mechanical stress and possible fabrication imperfections. Measurement results for a low-offset basic VHS in planar state show a sensitivity of 59 ± 1 V(AT)-1 in voltage mode and of 8 ± 0.1 %T-1 in current mode.
international symposium on circuits and systems | 2014
Hadi Heidari; Edoardo Bonizzoni; Umberto Gatti; Franco Maloberti
A magnetic Hall sensor working in the current-mode is presented. The proposed sensing device is composed by two Hall plates able to provide a differential current at the output nodes. The sensor, fabricated in a standard 0.18-μm CMOS technology, uses the spinning-current technique to compensate for the offset and obtains a sensitivity I<sub>Hall</sub>/(B⊥I<sub>bias</sub>) better than 0.02 T<sup>-1</sup> for magnetic fields ranging from 0 to 10 mT.
conference on ph.d. research in microelectronics and electronics | 2013
Hadi Heidari; Umberto Gatti; Edoardo Bonizzoni; Franco Maloberti
The performances of a current-mode Hall sensor featuring output current signals are discussed. The current-mode approach is analyzed by applying for first time to our best knowledge the spinning current technique to Hall plate working in current-mode to eliminate offset and 1/f noise. Among different geometries that have been studied and simulated using COMSOL MultiphysicsTM, cross-shaped model displayed the lowest noise and residual offset and the best sensitivity. The COMSOL results determined a behavioral model implemented in Verilog-A for simulations in the Cadence environment. Simulations results achieved in COMSOL and in Cadence environment show the potentiality, thus demonstrating the effectiveness of the approach, for a possible use of the device with remarkable performances.
IEEE Transactions on Electron Devices | 2017
Anastasios Vilouras; Hadi Heidari; Shoubhik Gupta; Ravinder Dahiya
The field of flexible electronics is rapidly evolving. The ultrathin chips are being used to address the high-performance requirements of many applications. However, simulation and prediction of changes in response of device/circuit due to bending induced stress remains a challenge as of lack of suitable compact models. This makes circuit designing for bendable electronics a difficult task. This paper presents advances in this direction, through compressive and tensile stress studies on transistors and simple circuits such as inverters with different channel lengths and orientations of transistors on ultrathin chips. Different designs of devices and circuits in a standard CMOS 0.18-
international solid-state circuits conference | 2016
Ka-Meng Lei; Hadi Heidari; Pui-In Mak; Man-Kay Law; Franco Maloberti; Rui Paulo Martins
\mu \text{m}
IEEE Transactions on Circuits and Systems | 2016
Shoubhik Gupta; Hadi Heidari; Anastasios Vilouras; Leandro Lorenzelli; Ravinder Dahiya
technology were fabricated in two separated chips. The two fabricated chips were thinned down to
conference on ph.d. research in microelectronics and electronics | 2015
Hadi Heidari; Nicoleta Wacker; S. Roy; Ravinder Dahiya
20~\mu \text{m}
ieee sensors | 2014
Hadi Heidari; Edoardo Bonizzoni; Umberto Gatti; Franco Maloberti
using standard dicing-before-grinding technique steps followed by post-CMOS processing to obtain sufficient bendability (20-mm bending radius, or 0.05% nominal strain). Electrical characterization was performed by packaging the thinned chip on a flexible substrate. Experimental results show change of carrier mobilities in respective transistors, and switching threshold voltage of the inverters during different bending conditions (maximum percentage change of 2% for compressive and 4% for tensile stress). To simulate these changes, a compact model, which is a combination of mathematical equations and extracted parameters from BSIM4, has been developed in Verilog-A and compiled into Cadence Virtuoso environment. The proposed model predicts the mobility variations and threshold voltage in compressive and tensile bending stress conditions and orientations, and shows an agreement with the experimental measurements (1% for compressive and 0.6% for tensile stress mismatch).