Hae-Jun Seo

A design of automatic current limit block for OLED display driver IC

The content in terms of ACL function which adjusts the brightness automatically as a function related to an OLED driver IC design of QVGA(320×240) is presented in this paper. ACL function adjusts luminance automatically as the brightness of adjacent circumstance and unnecessary power consumption of display panel can be reduced. Verification method is that original image is applied to ACL function and compare original image and result image.

Three-Dimensional stacked memory system for defect tolerance

This paper presents a method for constructing a memory system using defective memory chips comprising faulty storage blocks. The three-dimensional memory system introduced here employs a die-stacked structure of faulty memory chips. Signals lines passing through the through-silicon-vias (TSVs) connect chips in the defect tolerant structure. Defective chips are classified into several groups each group comprising defective chips having faulty blocks at the same location. A defect tolerant memory system is constructed using chips from different groups. Defect-free storage blocks from spare chips replace faulty blocks using additional routing circuitry. The number of spare memory chips for defect tolerance is s=

A Very Low Cost BCH Decoder for High Immunity of On-Chip Memories

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High Accurate Creep Compensation of the Loadcell using the Strain Gauge

( k × n ) / ( m --- k )

A Design of XOR Cell with Optimized Ground-less XNOR Circuit

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A Novel Integrated DC-DC Converter with High Efficient Charge Pump for Mobile Applications

to make a system defect tolerant for (n + s) chips with k faulty blocks among m independently addressable blocks.

High Efficient Charge Pump circuit for Poly-Si TFT LCD

BCH(Bose-Chaudhuri-Hoquenbhem) code, a type of block codes-cyclic codes, has very strong error-correcting ability which is vital for performing the error protection on the memory system. BCH code has many kinds of dual algorithms, PGZ(Pererson-Gorenstein-Zierler) algorithm out of them is advantageous in view of correcting the errors through the simple calculation in t value. However, this is problematic when this becomes 0 (divided by zero) in case ν ≠ t. In this paper, the circuit would be simplified by suggesting the multi-mode hardware architecture in preparation that v were 0~3. First, production cost would be less thanks to the smaller number of gates. Second, lessening power consumption could lengthen the recharging period. The very low cost and simple datapath make our design a good choice in small-footprint SoC(System on Chip) as ECC(Error Correction Code/Circuit) in memory system.