Tae-Won Cho

Efficient Multi-Touch Detection Algorithm for Large Touch Screen Panels

Large mutual capacitance touch screen panels (TSP) are susceptible to display and ambient noise. This paper presents a multi-touch detection algorithm using an efficient noise compensation technique for large mutual capacitance TSPs. The sources of noise are presented and analyzed. The algorithm includes the steps to overcome each source of noise. The algorithm begins with a calibration technique to overcome the TSP mutual capacitance variation. The algorithm also overcomes the shadow effect of a hand close to TSP and mutual capacitance variation by dynamic threshold calculations. Time and space filters are also used to filter out ambient noise. The experimental results were used to determine the system parameters to achieve the best performance.

Efficient algorithm for accurate touch detection of large touch screen panels

Large mutual capacitance touch screen panels (TSP) are susceptible to display and ambient noise. This paper presents a multi-touch detection algorithm using an efficient noise compensation technique for large mutual capacitance TSPs. The algorithm starts with a calibration technique to overcome TSP mutual capacitance variation. It also overcomes the shadow effect of a hand close to TSP and mutual capacitance variation by applying dynamic threshold calculations. Time and space filters are also used to filter out noise. Experimental results are used to determine system parameters for best performance.

Voltage shifting double integration circuit for high sensing resolution of large capacitive touch screen panels

We propose a new touch screen sensing circuit based on voltage shifting double integration scheme for large touch screen panels. The proposed circuit increases the sensing resolution by shifting integrated signal, while reducing the detection time by integrating both edges of sense signals. We implemented the proposed technique in FPGA and analog circuit with touch detection software. Experiments show that the proposed circuit improves both the touch performance and frame rate - key requirements for large touch screen controllers.

A sequential triggering technique in cascaded current source for low power 12‐b D/A converter

Purpose – The purpose of this paper is to introduce a low power digital‐to‐analog converter (DAC) by using a sequential triggering technique in cascaded current source.Design/methodology/approach – The block of current cell consists of current switch and source. A sequential switching on process is implemented with the current triggering technique in source. An experiment of 12‐b 150‐MS/s DAC has been integrated in a single‐poly four‐metal 0.35 μm CMOS process.Findings – Compared with conventional cell array in 12‐b 150‐MS/s DAC, the proposed cell array shows that more than 30 percent of power consumption is reduced in full digital bit operation with allowable linearity error of 0.4 LSB.Originality/value – This paper presents a new operation method of cell array in a current‐steering digital‐to‐analog converter (DAC) to reduce the power consumption significantly.

New modeling technique for memristor devices to cover deviation from memristive theory

Behavior of metal-oxide junctions has been addressed as a memristive behavior after 2008. This behavior is not exactly matched with memristive behavior. Extension of memristive theory is needed to match device behavior. In this paper, we present a modeling technique to model these junctions and show how and why their behavior is not exactly memristive behavior. Simulation results verify the proposed model and fit the measurement results.

Memristance and memcapacitance modeling of thin film devices showing memristive behavior

In 2008, the fourth passive element “Memristor” was implemented as a device having both passivity and nonvolatile properties opening the way into new possibilities in the design and fabrication of innovative memory, arithmetic and logic architectures. Nano-features and ionic transport mechanism inherent in memristor device introduce new challenges into modeling, characterization and, in particular, in the related circuit simulation needs with system constructs. Therefore, in this paper, we analyze memristor device fundamentally to characterize the memristance paying particular attention to the hidden memcapacitance effect. Our proposed macro-model modifies takes into account some of the non ideal effects like tunneling current and the hidden memcapacitor constructed across non conducting materials. The model provides the insight for building a device as either memristive or memcapacitive system. The simulation results have been compared with HP published data which show good agreement.

Three-Dimensional stacked memory system for defect tolerance

This paper presents a method for constructing a memory system using defective memory chips comprising faulty storage blocks. The three-dimensional memory system introduced here employs a die-stacked structure of faulty memory chips. Signals lines passing through the through-silicon-vias (TSVs) connect chips in the defect tolerant structure. Defective chips are classified into several groups each group comprising defective chips having faulty blocks at the same location. A defect tolerant memory system is constructed using chips from different groups. Defect-free storage blocks from spare chips replace faulty blocks using additional routing circuitry. The number of spare memory chips for defect tolerance is s=

A Very Low Cost BCH Decoder for High Immunity of On-Chip Memories

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A Fast Sensing Method using Concurrent Driving and Sequential Sensing for Large Capacitance Touch Screens

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Modeling of Memristive and Memcapacitive Behaviors in Metal-Oxide Junctions

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