Hafiz Md. Hasan Babu

Efficient approaches for designing reversible Binary Coded Decimal adders

Reversible logic has become one of the most promising research areas in the past few decades and has found its applications in several technologies; such as low-power CMOS, nanocomputing and optical computing. This paper presents improved and efficient reversible logic implementations for Binary Coded Decimal (BCD) adder as well as Carry Skip BCD adder. It has been shown that the modified designs outperform the existing ones in terms of number of gates, number of garbage outputs, delay, and quantum cost. In order to show the efficiency of the proposed designs, lower bounds of the reversible BCD adders in terms of gates and garbage outputs are proposed as well.

Design of a compact reversible binary coded decimal adder circuit

Reversible logic is an emerging research area and getting remarkable interests over the past few years. Interest is sparked in reversible logic by its applications in several technologies, such as quantum, optical, thermodynamics and adiabatic CMOS. This paper represents a synthesis method to realize reversible binary coded decimal adder circuit. Firstly, a reversible full-adder circuit has been proposed that shows the improvement over the two existing circuits. A lower bound is also proposed for the reversible full-adder circuit on the number of garbage outputs (bits needed for reversibility, but not required for the output of the circuit). After that, a final improvement is presented for the reversible full-adder circuit. Finally, a new reversible circuit has been proposed, namely reversible binary coded decimal (BCD) adder, which is the first ever proposed in reversible logic synthesis. In the way to propose reversible BCD adder, a reversible n-bits parallel adder circuit is also shown. Lower bounds for the reversible BCD adder in terms of number of garbage outputs and number of reversible gates are also shown. Delay has also been calculated for each circuit.

Design of a reversible binary coded decimal adder by using reversible 4-bit parallel adder

In this paper, we have proposed a design technique for the reversible circuit of binary coded decimal (BCD) adder. The proposed circuit has the ability to add two 4-bits binary variables and it transforms the addition into the appropriate BCD number with efficient error correcting modules where the operations are reversible. We also show that the proposed design technique generates the reversible BCD adder circuit with minimum number of gates as well as the minimum number of garbage outputs.

An Efficient Design of a Reversible Barrel Shifter

The key objective of today’s circuit design is to increase the performance without the proportional increase in power consumption. In this regard, reversible logic has become an immensely promising technology in the field of low power computing and designing. On the other hand, data shifting and rotating are required in many operations such as arithmetic and logical operations, address decoding and indexing etc. In this consequence, barrel shifters, which can shift and rotate multiple bits in a single cycle, have become a common design choice for high speed applications. For this reason, this paper presents an efficient design of a reversible barrel shifter. It has also been shown that the new circuit outperforms the previously proposed one in terms of number of gates, number of garbage outputs, delay and quantum cost.

Efficient Design of Shift Registers Using Reversible Logic

Reversible shift registers are required to construct reversible memory circuits. This paper presents novel designs of reversible shift registers such as serial-in serial-out (SISO), serial-in parallel-out (SIPO), parallel-in serial-out (PISO), parallel-in parallel-out (PIPO) and universal shift registers. In order to show the efficiency, lower bounds of the proposed designs are shown in terms of number of gates required, garbage outputs produced and quantum cost needed. As far as it is known, this is the first attempt to apply reversible logic to implement shift registers (except SISO). Appropriate theorems and lemmas are presented to clarify the proposed designs. The contribution of this paper will engender a new thread of research in the field of reversible sequential circuits.

Novel reversible division hardware

This paper presents a novel design of sequential division circuit using reversible logic, which is a promising research area nowadays. The proposed hardware has its application in the design of reversible arithmetic logic unit. In order to show the efficiency, lower bounds of the proposed design are shown in terms of number of gates required, garbage outputs produced and quantum cost needed. As far as it is known, this is the first attempt to apply reversible logic to implement division hardware. As the works in the field of reversible logic has only started to bloom, the contribution of this paper will engender a new thread of research in the field of reversible division circuit.

A Novel Approach to Design BCD Adder and Carry Skip BCD Adder

Reversible logic has become one of the most promising research areas in the past few decades and has found its applications in several technologies; such as low power CMOS, nanocomputing and optical computing. This paper presents improved and efficient reversible logic implementations for Binary Coded Decimal (BCD) adder as well as Carry Skip BCD adder. It has been shown that the modified designs outperform the existing ones in terms of number of gates, number of garbage output and delay.

A Low Power Fault Tolerant Reversible Decoder Using MOS Transistors

This paper demonstrates the reversible logic synthesis for the n-to-2n decoder, where n is the number of data bits. The circuits are designed using only reversible fault tolerant Fredkin and Feynman double gates. Thus, the entire scheme inherently becomes fault tolerant. Algorithm for designing the generalized decoder has been presented. In addition, several lower bounds on the number of constant inputs, garbage outputs and quantum cost of the reversible fault tolerant decoder have been proposed. Transistor simulations of the proposed decoder are shown using standard p-MOS 901 and n-MOS 902 model with delay of 0.030 ns and 0.12 m channel length, which proved the functional correctness of the proposed circuits. The comparative results show that the proposed design is much better in terms of quantum cost, delay, hardware complexity and has significantly better scalability than the existing approach.

Approach to design a compact reversible low power binary comparator

Reversible logic has captured significant attention in recent time as reducing power consumption is the main concern of digital logic design. It consumes less power by recovering bit loss from its unique input-output mapping. In this study, the authors propose a reversible low power n -bit binary comparator. An algorithm is presented for constructing a compact reversible n -bit binary comparator circuit. The authors also propose two new reversible gates, namely, Babu-Jamal-Saleheen (BJS) and Hasan-Lafifa-Nazir (HLN) gates, to optimise the comparator. In addition, several theorems on the numbers of gates, garbage outputs, quantum cost, ancilla input, power, delay and area of the reversible n -bit comparator have been presented. The simulation results of the proposed comparator show that the circuit works correctly and gives significantly better performance than the existing ones. The comparative study shows that, as an example, for a 64-bit comparator, the proposed design achieves the improvement of 24.4% in terms of number of gates, 19.9% in terms of garbage outputs, 7.7% in terms of quantum cost, 25.77% in terms of area and 3.43% in terms of power over the existing best one. Area and power analysis also show that the proposed design is the most compact as well as a low power circuit.

An efficient approach for designing a reversible fault tolerant n-bit carry look-ahead adder

Reversible logic has captured significant attention in recent time as reducing power consumption is the main concern of digital logic design. It consumes less power by recovering bit loss from its unique input-output mapping. This paper presents the design of an optimal reversible fault tolerant carry look-ahead adder. We present an algorithm to design a generalized n-bit carry look-ahead adder, where n is the number of bits of the operands. A new technique to calculate the quantum gate complexity of quantum circuits has also been proposed in the paper. In addition, several theorems on the numbers of garbage outputs, quantum cost, quantum gate complexity and delay of the fault tolerant reversible carry look-ahead adder have been presented to show its optimality. Simulation using Microwind DSCH software has been shown to verify the correctness of the function of the proposed carry look-ahead adder. The comparative study shows that the proposed design is much better than the existing approach considering all the efficiency parameters of reversible circuit design which includes numbers of gates, quantum cost, delay, quantum gate complexity and garbage outputs. The proposed 8-bit reversible fault tolerant carry look-ahead adder improves 94.9% on the number of gates, 92.4% on the quantum cost, 93.2% on the garbage outputs and 14.5% on the delay than the existing design.