Lafifa Jamal

Efficient Design of Shift Registers Using Reversible Logic

Reversible shift registers are required to construct reversible memory circuits. This paper presents novel designs of reversible shift registers such as serial-in serial-out (SISO), serial-in parallel-out (SIPO), parallel-in serial-out (PISO), parallel-in parallel-out (PIPO) and universal shift registers. In order to show the efficiency, lower bounds of the proposed designs are shown in terms of number of gates required, garbage outputs produced and quantum cost needed. As far as it is known, this is the first attempt to apply reversible logic to implement shift registers (except SISO). Appropriate theorems and lemmas are presented to clarify the proposed designs. The contribution of this paper will engender a new thread of research in the field of reversible sequential circuits.

Novel reversible division hardware

This paper presents a novel design of sequential division circuit using reversible logic, which is a promising research area nowadays. The proposed hardware has its application in the design of reversible arithmetic logic unit. In order to show the efficiency, lower bounds of the proposed design are shown in terms of number of gates required, garbage outputs produced and quantum cost needed. As far as it is known, this is the first attempt to apply reversible logic to implement division hardware. As the works in the field of reversible logic has only started to bloom, the contribution of this paper will engender a new thread of research in the field of reversible division circuit.

Approach to design a compact reversible low power binary comparator

Reversible logic has captured significant attention in recent time as reducing power consumption is the main concern of digital logic design. It consumes less power by recovering bit loss from its unique input-output mapping. In this study, the authors propose a reversible low power n -bit binary comparator. An algorithm is presented for constructing a compact reversible n -bit binary comparator circuit. The authors also propose two new reversible gates, namely, Babu-Jamal-Saleheen (BJS) and Hasan-Lafifa-Nazir (HLN) gates, to optimise the comparator. In addition, several theorems on the numbers of gates, garbage outputs, quantum cost, ancilla input, power, delay and area of the reversible n -bit comparator have been presented. The simulation results of the proposed comparator show that the circuit works correctly and gives significantly better performance than the existing ones. The comparative study shows that, as an example, for a 64-bit comparator, the proposed design achieves the improvement of 24.4% in terms of number of gates, 19.9% in terms of garbage outputs, 7.7% in terms of quantum cost, 25.77% in terms of area and 3.43% in terms of power over the existing best one. Area and power analysis also show that the proposed design is the most compact as well as a low power circuit.

An efficient approach for designing a reversible fault tolerant n-bit carry look-ahead adder

Reversible logic has captured significant attention in recent time as reducing power consumption is the main concern of digital logic design. It consumes less power by recovering bit loss from its unique input-output mapping. This paper presents the design of an optimal reversible fault tolerant carry look-ahead adder. We present an algorithm to design a generalized n-bit carry look-ahead adder, where n is the number of bits of the operands. A new technique to calculate the quantum gate complexity of quantum circuits has also been proposed in the paper. In addition, several theorems on the numbers of garbage outputs, quantum cost, quantum gate complexity and delay of the fault tolerant reversible carry look-ahead adder have been presented to show its optimality. Simulation using Microwind DSCH software has been shown to verify the correctness of the function of the proposed carry look-ahead adder. The comparative study shows that the proposed design is much better than the existing approach considering all the efficiency parameters of reversible circuit design which includes numbers of gates, quantum cost, delay, quantum gate complexity and garbage outputs. The proposed 8-bit reversible fault tolerant carry look-ahead adder improves 94.9% on the number of gates, 92.4% on the quantum cost, 93.2% on the garbage outputs and 14.5% on the delay than the existing design.

Design of a compact reversible fault tolerant field programmable gate array: A novel approach in reversible logic synthesis

Abstract This paper demonstrates the reversible fault tolerant logic synthesis for the Field Programmable Gate Array (FPGA) and its realization using MOS transistors. Algorithms to design a compact reversible fault tolerant n-to- 2 n decoder, 4n-to-n multiplexers, a random access memory and a Plessey logic block of the FPGA have been presented. In addition, several lower bounds on the numbers of garbage outputs, constant inputs and quantum cost of the FPGA have been proposed. The comparative results show that the proposed design is much better in terms of gate count, garbage outputs, quantum cost, delay, and hardware complexity than the existing approaches.

An efficient approach for designing and minimizing reversible programmable logic arrays

Reversible computing dissipates zero energy in terms of information loss at input and also it can detect error of circuit by keeping unique input-output mapping. In this paper, we have proposed a cost effective design of Reversible Programmable Logic Arrays (RPLAs) which is able to realize multi-output ESOP (Exclusive-OR Sum-Of-Product) functions by using a cost effective 3x3 reversible gate, called MG (MUX Gate). Also a new algorithm has been proposed for the calculation of critical path delay of reversible PLAs. The minimization processes consist of algorithms for ordering of output functions followed by the ordering of products. Five lower bounds on the numbers of gates, garbages and quantum costs of reversible PLAs are also proposed. Finally, we have compared the efficiency of proposed design with the existing one by providing benchmark functions analysis. The experimental results show that the proposed design outperforms the existing one in terms of numbers of gates, garbages, quantum costs and delay.

Efficient approaches to design a reversible floating point divider

In this paper, we propose a reversible n-bit divider, where n is the number of bits of the operands of dividend. Two approaches for constructing a compact reversible divider have been presented here. The first approach uses conventional division array and the second approach uses high speed division array. Both of the approaches can handle floating point numbers. Several theorems on the numbers of gates, garbage outputs and quantum cost of the reversible n-bit divider have been shown. The comparative study shows that the proposed designs can work with fractional numbers where as existing designs can not. Proposed designs are also much better than the existing approaches considering all the efficiency parameters of reversible logic design which includes numbers of gates used, quantum cost and garbage outputs.

SAGLET-Secure agent communication model

Mobile agent offers a new programming paradigm in which a program can move from one node to another node in a network. Since data as well as code move at the same time, security issue becomes more important than traditional RPC system. To overcome the security hurdles, this paper presents a new model based on existing Aglets architecture. A new service agent along with a policy file is incorporated with the existing Aglets architecture. This novel service agent which controls & co-ordinates all communication between the agent and the platform provides an extra layer of security by a set of API. This extra layer of security in Aglets will enhance the overall security of the platform.

An optimal design of a fault tolerant reversible multiplier

One of the most challenging issues in circuit design is power consumption. Reversible logic is one of the ways for power optimization. In this paper, we propose an optimal design of a fault tolerant reversible n×n multiplier circuit, where n is the number of bits of the operands of multiplier. Two algorithms have been presented to construct the Partial Product Generation (PPG) circuit and the Multi-Operand Addition (MOA) circuit of the proposed multiplier. We also propose a new fault tolerant reversible gate, namely, LMH gate, to produce an optimal multiplier. In addition, several theorems on the numbers of gates, garbage outputs and quantum cost of the fault tolerant reversible multiplier have been presented to show its optimality. The comparative study shows that the proposed design is much better than the existing approaches considering all the efficiency parameters of reversible logic design which includes numbers of gates, garbage outputs, quantum cost and constant inputs; e.g., for a 4×4 multiplier, the proposed design achieves the improvement of 26.32% in terms of number of gates, 12.5% in terms of garbage outputs, 17% in terms of quantum cost and 20.97% in terms of constant inputs over the existing latest approach.

Design of a Fault Tolerant Reversible Compact Unidirectional Barrel Shifter

This paper demonstrates reversible logic synthesis for (n, k) unidirectional logarithmic barrel shifters, where n is the number of data bits and k=log2n. The circuits are designed using only reversible fault tolerant Fredkin gates. Thus, the entire scheme inherently becomes fault tolerant. Several lower bounds on the numbers of garbage outputs and constant inputs have been proposed. The comparative results show that the proposed method is much better in terms of numbers of gates, garbage outputs, quantum cost, hardware complexity and has significantly better scalability than the existing approaches.