Partha Sarathi Gupta
Indian Institute of Engineering Science and Technology, Shibpur
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Publication
Featured researches published by Partha Sarathi Gupta.
IEEE Transactions on Electron Devices | 2015
Sayan Kanungo; Sanatan Chattopadhyay; Partha Sarathi Gupta; Hafizur Rahaman
In this paper, a short-gate tunneling-field-effect-transistor (SG-TFET) structure has been investigated for the dielectrically modulated biosensing applications in comparison with a full-gate tunneling-field-effect-transistor structure of similar dimensions. This paper explores the underlying physics of these architectures and estimates their comparative sensing performance. The sensing performance has been evaluated for both the charged and charge-neutral biomolecules using extensive device-level simulation, and the effects of the biomolecule dielectric constant and charge density are also studied. In SG-TFET architecture, the reduction of the gate length enhances its drain control over the band-to-band tunneling process and this has been exploited for the detection, resulting to superior drain current sensitivity for biomolecule conjugation. The gate and drain biasing conditions show dominant impact on the sensitivity enhancement in the short-gate biosensors. Therefore, the gate and drain bias are identified as the effective design parameters for the efficiency optimization.
advances in computing and communications | 2013
Pranab Roy; Hafizur Rahaman; Partha Sarathi Gupta; Parthasarathi Dasgupta
Digital microfluidic biochip (DFMB) systems have been developed as a promising platform for Lab-on-chip systems that manipulate individual droplet of chemicals on a 2D planar array of electrodes. Because of the safety critical nature of the applications these devices are intended for high reliability and thereby dependability becomes a major issue for the design of DMFBs. Therefore, such devices are required to be tested frequently both off-line (e.g., post-manufacturing) and prior to each assay execution. Under both scenarios, testing is accomplished by routing one or more test droplets across the chip and recording their arrival at the scheduled destination. In this paper, we have proposed a new design of a droplet motion detector based on capacitive sensing, which can be manufactured with the cell electrodes for detection of the presence (arrival) of a droplet at a predetermined location. Using this sensor, we have further proposed a customized testing technique for a specified layout with an objective of 1) optimizing the total number of test droplets for testing a particular bioassay, 2) optimizing the number of dispensers, 3) minimizing the overall test completion time, 4) detection of a specific segment at fault within the given layout, and 5) optimizing the number of locations where the detectors are to be activated. The test simulation has been carried out on two testbenches of Benchmark suite III and the results are found to be encouraging compared to the existing methods.
international conference on computers and devices for communication | 2012
Sayan Kanungo; Hafizur Rahaman; Partha Sarathi Gupta; Partha Sarathi Dasgupta
An analytical model for the 2D potential distribution in sub-threshold regime of operation of a SOI TFET structure under the assumption of a sinusoidal potential distribution in the direction perpendicular to the gate in the middle portion of the channel is developed. Role of any charge on the channel potential is neglected. The model predicts the transfer characteristics of the device with reasonable accuracy.
international conference on computers and devices for communication | 2012
Sayan Kanungo; Hafizur Rahaman; Partha Sarathi Gupta; Partha Sarathi Dasgupta
This work presents an extensive simulation study on different design parameters of an Extended Source Ultra Thin Body Double-Gated Tunneling Field Effect Transistor structure. The study investigates the effects of different device design parameter variations on electrical parameters like: sub-threshold swing, trans-conductance, ON-state current and OFF-state current. Finally an optimum structure for Extended Source Ultra Thin Body Double-Gated Tunneling Field Effect Transistor has been derived from the simulation study, with encouraging results for parameters of interest.
Journal of Applied Physics | 2016
Partha Sarathi Gupta; Hafizur Rahaman; Kunal Sinha; Sanatan Chattopadhyay
In this article, we propose a novel optoelectronic band-to-band tunnel field effect transistor with a Si photo-gate, for multi-spectral sensing of near-infrared light in the wavelength range of 0.7 μm–1 μm. Based on the line tunneling approach, a drain current model has been developed to illustrate the device operating principle. The model incorporates the effect of photo-generation in the photo-gate in terms of the resulting photo-voltage. Good agreement with device simulation results indicates overall correctness of the developed model. The spectral response of the device has been studied in terms of its input and output characteristics, and the spectral sensitivity has been defined in terms of the change in current, in response to the change in the illumination wavelength. The proposed device can resolute closely spaced spectral lines (∼100 nm) in the wavelength range of 0.7 μm–1 μm, due to the combined effects of steep average sub-threshold swing of ∼19 mV/dec, over five current decades, and current m...
vlsi design and test | 2012
Partha Sarathi Gupta; Sayan Kanungo; Hafizur Rahaman; Partha Sarathi Dasgupta
This paper presents a modified UTB SOI TFET structure and a thorough simulation study of various device design parameters on this structure.
international conference on computing electronics and electrical technologies | 2012
Partha Sarathi Gupta; Sayan Kanungo; Hafizur Rahaman; Partha Sarathi Dasgupta
This paper presents a novel design scheme to reduce the short channel effects effectively in deep sub-micron MOSFET design. This scheme shows excellent improvement in the off-state current and proves to be very effective in controlling channel length modulation in nano-scale device design. This paper also proposes a subsequent theory to explain the effect of the design scheme on device characteristics supported by a through simulation study.
international conference on communications | 2012
Partha Sarathi Gupta; Madhuchhanda Brahma; Jayita Das; Debasree Burman; Hafizur Rahaman; Partha Sarathi Dasgupta
The Sandwiched Barrier Tunnel FET is a promising device for low power applications. It shows a steep subthreshold slope and a CMOS compatible high ON-STATE current, (Ion). In this paper we present a simulation study to investigate the dependence of key device metrics on various structural parameters. We also present a simple model for the subthreshold current assuming an extreme retrograde doping profile. The assumption made, is justified through simulation results.
international conference on devices circuits and systems | 2014
Sayan Kanungo; Partha Sarathi Gupta; Hafizur Rhaman
International Journal of Applied Physics and Mathematics | 2012
Partha Sarathi Gupta; Sayan Kanungo; Hafizur Rahaman; Kunal Sinha; Partha Sarathi Dasgupta