Haider A. F. Almurib

SHE–PWM Cascaded Multilevel Inverter With Adjustable DC Voltage Levels Control for STATCOM Applications

This paper presents a new multilevel selective harmonic elimination pulse-width modulation (MSHE-PWM) technique for transformerless static synchronous compensator (STATCOM) system employing cascaded H-bridge inverter (CHI) configuration. The proposed MSHE-PWM method optimizes both the dc-voltage levels and the switching angles, enabling more harmonics to be eliminated without affecting the structure of the inverter circuit. The method provides constant switching angles and linear pattern of dc-voltage levels over the modulation index range. This in turns eliminates the tedious steps required for manipulating the offline calculated switching angles and therefore, easing the implementation of the MSHE-PWM for dynamic systems. Although the method relies on the availability of the variable dc-voltage levels which can be obtained by various topologies, however, the rapid growth and development in the field of power semiconductor devices led to produce high-efficiency dc-dc converters with a relatively high-voltage capacity and for simplicity, a buck dc-dc converter is considered in this paper. Current and voltage closed loop controllers are implemented for both the STATCOM and the buck converter to meet the reactive power demand at different loading conditions. The technique is further compared with an equivalent conventional carrier-based pulse-width modulation to illustrate its enhanced characteristics. The effectiveness and the theoretical analysis of the proposed approach are verified through both simulation and experimental studies.

A Coordinated Design of PSSs and UPFC-based Stabilizer Using Genetic Algorithm

This paper details a new coordinated design between power system stabilizers (PSSs) and a unified power flow controller (UPFC) using genetic algorithms (GAs). A GA scheme determines the optimal location for a UPFC while tuning its control parameters, resulting in the optimization of the quantity, parameters, and locations of PSSs under different operating conditions. The problem is formulated as a multiobjective optimization problem in order to maximize the damping ratio(s) of electromechanical modes, matching different numbers of PSSs with a UPFC. The approach is successfully tested on the New England-New York interconnected system (a 16-machine and 68-bus system), proving its effectiveness in damping local and interarea modes of oscillations.

A New Reactive Current Reference Algorithm for the STATCOM System Based on Cascaded Multilevel Inverters

This paper presents a simple controller integrating a new reactive current reference algorithm for enhancing the transient performance of static synchronous compensator (STATCOM). A multilevel cascaded inverter with separated dc capacitors which is driven by carrier-based pulse width modulation is used to implement the STATCOM. The voltage across each dc-link capacitor is regulated by the rotated switching swapping scheme. In this paper, the STATCOM is controlled to provide both reactive power (VAR) compensation and grid power factor correction at the point of common coupling with a dynamically varying reactive load system. The proposed algorithm enhances the transient performance of the closed-loop system with only proportional controller and minimizes the STATCOM reactive current ripples. STATCOM based on a five-level cascaded inverter is presented in this paper and the performance of the proposed controller is investigated through various simulation studies using MATLAB/Simulink software for both steady state and transient conditions. A laboratory prototype is also developed to verify the simulation results where a good match between simulation and experimental results is achieved.

A coordinated design of PSSs and UPFC-based stabilizer using Genetic Algorithm

This paper details a new coordinated design between power system stabilizers (PSSs) and a unified power flow controller (UPFC) using genetic algorithms (GAs). A GA scheme determines the optimal location for a UPFC while tuning its control parameters, resulting in the optimization of the quantity, parameters, and locations of PSSs under different operating conditions. The problem is formulated as a multiobjective optimization problem in order to maximize the damping ratio(s) of electromechanical modes, matching different numbers of PSSs with a UPFC. The approach is successfully tested on the New England-New York interconnected system (a 16-machine and 68-bus system), proving its effectiveness in damping local and interarea modes of oscillations.

Inexact designs for approximate low power addition by cell replacement

This paper proposes three designs of an inexact adder cell for approximate computing. These cells require a substantially smaller number of transistors compared to an exact full adder cell as well as known inexact designs. These inexact cells are simulated at 45 nm and compared with respect to circuit based metrics (such as energy consumption, delay, complexity and energy delay product) as well as error metrics (such as error rate). The replacement of exact cells with inexact cells such as the ones proposed in this manuscript in a ripple carry adder is evaluated to assess by exhaustive simulation different metrics for approximate computing; image addition is then pursued as application. These results show that among existing inexact cells found in the technical literature, the proposed designs consume the least power and have superior performance in terms of delay, switching capacitance and error measures for image quality and processing.

A novel design of a memristor-based look-up table (LUT) for FPGA

This paper presents a novel scheme for a memristor-based look-up table (LUT); in this scheme the states of the unselected memristors are unaffected by WRITE/READ operations. Therefore, it addresses the prevalent problems associated with nano crossbars, such as the write half-select and sneak path currents. In the proposed scheme the memristors are connected in rows and columns, while the columns are isolated. The new scheme is simulated using LTSPICE IV and extensive results are presented with respect to the WRITE and READ operations. In addition, the performance improvement of the proposed method is compared with previous LUT schemes using memristors as well as SRAM. The results show that proposed scheme is significantly better in terms of delay and Energy Delay Product (EDP) for both the WRITE and READ operations.

A memristor-based LUT for FPGAs

This paper presents a memristor-based Look-Up Table (LUT) for FPGAs. The proposed memory utilizes memristors as storage elements and NMOS transistors for selection. New WRITE and READ operations are proposed; the proposed LUT requires no additional circuit to handle the WRITE 1 (0) operation for both the word and bit lines. Also, it requires a RESTORE pulse only for the READ 0 operation. The WRITE operation of the proposed method requires three power lines (+Vdd, -Vdd and Gnd) and a RESTORE pulse only for the READ 0 operation, thus accomplishing savings of 25% for both the number of power lines and READ time when compared to previous methods. The proposed LUT is simulated using LTSPICE and extensive simulation results are presented with respect to different operational features, such as normalized state parameter of the memristance, pulse width, LUT size and MOSFET feature size. These results show that the proposed scheme offers superior performance compared with other existing memristor-based schemes found in the technical literature for FPGAs.

On the operational features and performance of a memristor-based cell for a LUT of an FPGA

This paper presents the detailed analysis of a memristor-based cell for a Look-Up Table (LUT) of a FPGA. The basic operational properties of this memristor-based cell are considered in depth. It shows that different from previous schemes, the ringing phenomenon of the so-called normalized state parameter does not affect data integrity. An extensive simulation based analysis of the two basic memory operations (READ and WRITE) and the corrective operation (RESTORE) is provided to show its substantial advantages. Moreover, the impact of varying different features of the memristor (range and dimension) and the feature size of the NMOS is evaluated for the resistive assessment at cell-level to show substantial improvements in terms of energy dissipation and READ/WRITE times.

Joint Torque Reduction of a Three Dimensional Redundant Planar Manipulator

Research on joint torque reduction in robot manipulators has received considerable attention in recent years. Minimizing the computational complexity of torque optimization and the ability to calculate the magnitude of the joint torque accurately will result in a safe operation without overloading the joint actuators. This paper presents a mechanical design for a three dimensional planar redundant manipulator with the advantage of the reduction in the number of motors needed to control the joint angle, leading to a decrease in the weight of the manipulator. Many efforts have been focused on decreasing the weight of manipulators, such as using lightweight joints design or setting the actuators at the base of the manipulator and using tendons for the transmission of power to these joints. By using the design of this paper, only three motors are needed to control any n degrees of freedom in a three dimensional planar redundant manipulator instead of n motors. Therefore this design is very effective to decrease the weight of the manipulator as well as the number of motors needed to control the manipulator. In this paper, the torque of all the joints are calculated for the proposed manipulator (with three motors) and the conventional three dimensional planar manipulator (with one motor for each degree of freedom) to show the effectiveness of the proposed manipulator for decreasing the weight of the manipulator and minimizing driving joint torques.

A review of autonomous multi-agent quad-rotor control techniques and applications

The theory analysis of this review is applied to the task of controlling and maneuvering the quad-rotor. The singular four rotor flying vehicle is designed, optimized and applied to the expanded multi-agent system. This produces an evaluation and discussion of the most common and lesser known control laws used to navigate the vehicle as it performs basic translational and rotational motions. Related works based on the complexity of successful collision avoidance and formation between multi-agent quad-rotors is evaluated. A comparison is made between the advantages and disadvantages of each design to allow an understanding of the current research in the field of the multi-agent four rotor flying vehicle. The achievements and applications of the intelligent multi-agent system are then addressed. Lastly, future prospects and challenges to overcome are suggested.