T. Nandha Kumar

Inexact designs for approximate low power addition by cell replacement

This paper proposes three designs of an inexact adder cell for approximate computing. These cells require a substantially smaller number of transistors compared to an exact full adder cell as well as known inexact designs. These inexact cells are simulated at 45 nm and compared with respect to circuit based metrics (such as energy consumption, delay, complexity and energy delay product) as well as error metrics (such as error rate). The replacement of exact cells with inexact cells such as the ones proposed in this manuscript in a ripple carry adder is evaluated to assess by exhaustive simulation different metrics for approximate computing; image addition is then pursued as application. These results show that among existing inexact cells found in the technical literature, the proposed designs consume the least power and have superior performance in terms of delay, switching capacitance and error measures for image quality and processing.

A novel design of a memristor-based look-up table (LUT) for FPGA

This paper presents a novel scheme for a memristor-based look-up table (LUT); in this scheme the states of the unselected memristors are unaffected by WRITE/READ operations. Therefore, it addresses the prevalent problems associated with nano crossbars, such as the write half-select and sneak path currents. In the proposed scheme the memristors are connected in rows and columns, while the columns are isolated. The new scheme is simulated using LTSPICE IV and extensive results are presented with respect to the WRITE and READ operations. In addition, the performance improvement of the proposed method is compared with previous LUT schemes using memristors as well as SRAM. The results show that proposed scheme is significantly better in terms of delay and Energy Delay Product (EDP) for both the WRITE and READ operations.

A memristor-based LUT for FPGAs

This paper presents a memristor-based Look-Up Table (LUT) for FPGAs. The proposed memory utilizes memristors as storage elements and NMOS transistors for selection. New WRITE and READ operations are proposed; the proposed LUT requires no additional circuit to handle the WRITE 1 (0) operation for both the word and bit lines. Also, it requires a RESTORE pulse only for the READ 0 operation. The WRITE operation of the proposed method requires three power lines (+Vdd, -Vdd and Gnd) and a RESTORE pulse only for the READ 0 operation, thus accomplishing savings of 25% for both the number of power lines and READ time when compared to previous methods. The proposed LUT is simulated using LTSPICE and extensive simulation results are presented with respect to different operational features, such as normalized state parameter of the memristance, pulse width, LUT size and MOSFET feature size. These results show that the proposed scheme offers superior performance compared with other existing memristor-based schemes found in the technical literature for FPGAs.

On the operational features and performance of a memristor-based cell for a LUT of an FPGA

This paper presents the detailed analysis of a memristor-based cell for a Look-Up Table (LUT) of a FPGA. The basic operational properties of this memristor-based cell are considered in depth. It shows that different from previous schemes, the ringing phenomenon of the so-called normalized state parameter does not affect data integrity. An extensive simulation based analysis of the two basic memory operations (READ and WRITE) and the corrective operation (RESTORE) is provided to show its substantial advantages. Moreover, the impact of varying different features of the memristor (range and dimension) and the feature size of the NMOS is evaluated for the resistive assessment at cell-level to show substantial improvements in terms of energy dissipation and READ/WRITE times.

A review of autonomous multi-agent quad-rotor control techniques and applications

The theory analysis of this review is applied to the task of controlling and maneuvering the quad-rotor. The singular four rotor flying vehicle is designed, optimized and applied to the expanded multi-agent system. This produces an evaluation and discussion of the most common and lesser known control laws used to navigate the vehicle as it performs basic translational and rotational motions. Related works based on the complexity of successful collision avoidance and formation between multi-agent quad-rotors is evaluated. A comparison is made between the advantages and disadvantages of each design to allow an understanding of the current research in the field of the multi-agent four rotor flying vehicle. The achievements and applications of the intelligent multi-agent system are then addressed. Lastly, future prospects and challenges to overcome are suggested.

Modeling of bipolar resistive switching of a nonlinear MISM memristor

This paper presents a novel mathematical model of the bipolar resistive switching (BRS) of the metal-insulator-semiconductor-metal (MISM) in a Pt/Ta2O5/TaO x /Pt memristor. The proposed model is based on quantum mechanics and describes the BRS behaviour based on electron band theory and the physical characteristics of the metal-insulator-semiconductor (MIS) system. It also includes the physical characteristics of the insulator layer. The novelty of the proposed model lies in incorporating the tunnelling probability factor (TPF) between the semiconductor and the metal layers and therefore demonstrating its effect on the conduction mechanism. In addition, the effect of continuous variation of the interface traps densities and the ideality factor during BRS is modelled using the semiconductor properties and the characteristics of the MIS system. Thus, the model emphasizes the dependency of the memristor current on the physical characteristics of the insulator layer. Moreover, the electric field equation for the active region is derived for the MISM structure which is used, together with the Mott and Gurney rigid point-ion model and the Joule heating effect, to model the oxygen ion migration mechanism. Finally, the model also demonstrates the self-limiting growth of the doped region. Extensive simulation is carried out on the proposed model and the results are correlated against the experimental data which show that the proposed model is in good agreement with the physical characteristics of the MISM memristor.

One-bit non-volatile memory cell using memristor and transmission gates

In recent researches, much emphasis has been placed in developing non-volatile memories as candidates for replacement of volatile memories. Apart from non-volatility, memristive devices also have high switching speed, low energy consumption, and small device size. In this article, a novel one-bit memory cell using two transmission gates and one memristor (2TG1M) is proposed. SPICE simulations were performed to compare energy requirements per one-bit memory cell between the proposed memory cell and the conventional volatile one-bit SRAM cell. Simulations show that the SRAM memory cell requires between 73.034 pJ and 12.433 nJ to retain logic information for 10 years, while the proposed memory cell requires less than 1 pJ to hold logic information for up to 10 years. The proposed memory cell is also simulated against the popular one transistor one memristor (1T1M) non-volatile memory cell to show faster switching speed by 1.5 times. This work concludes the advantages of the proposed 2TG1M nonvolatile memory cell against volatile memory in terms of energy requirements, and against non-volatile memory in terms of switching speed.

Scalable Application-Dependent Diagnosisof Interconnects of SRAM-Based FPGAs

This paper presents a new method for diagnosing (detection and location) multiple faults in an application-dependent interconnect of a SRAM-based FPGA. For fault detection, the proposed technique retains the original interconnect configuration and modifies the function of the LUTs using the new LUT programming function 1-Bit Sum Function (1-BSF); in addition, it utilizes features such as branches in the nets as well as the primary (unused) IOs of the FPGAs. The proposed method detects all possible stuck-at and bridging faults of all cardinalities in a single configuration; fault detection requires 1 + log2k test configurations for multiple stuck-at location and 2 + 2log2k additional test configurations to locate more than one pair-wise bridging faults (where k denotes the maximum combinational depth of the FPGA circuit). Following detection, the locations of multiple faults are hierarchically identified using the walking-1 test set and an adaptive approach for the interconnect structure. Net ordering independence is accomplished by utilizing features such as the presence of paths of nets that are either disjoint or joint between the primary input and at least one primary output. As validated by simulation on benchmark circuits, the proposed method scales extremely well for different Virtex FPGA families; this results in a significant reduction in the number of configurations for diagnosing multiple faults.

Improved SPICE model for Phase Change Memory cell

This paper presents an LTSpice model for a Phase Change Memory (PCM) cell that accurately simulate the temperature profile, the crystalline fraction and the resistance of the cell as a function of the programming pulse based on physical theories. The model is able to generate the I-V characteristics of a PCM cell, and precisely simulate the drift phenomenon of resistance and threshold voltage at the amorphous phase. The parameters in the model are calibrated with experimental data, and the exact duration of the programming pulse and OFF time are calculated to accurately assess the impact of time. The simulation results of the proposed PCM model are in close agreement with experimental results.

Testing a Nanocrossbar for Multiple Fault Detection

This paper proposes an approach for testing a nanocrossbar switch; fault detection is considered in the presence of faulty switches and nets (of a permanent nature only) in the crossbar. To ensure detection, a one-to-one (onto) relationship in the setting (programming) of the switches is established in each of the configurations of the crossbar. This is accomplished using a constant-sum transformation of the characteristic matrix of the crossbar by utilizing different graph algorithms in O(N4.5) where N is the matrix dimension. Matrix properties are related to graph algorithms to generate permutation matrices as corresponding to the configurations (phases) of the crossbar. The conditions by which multiple faults are detected by the modified counting sequence (as test set), are proved. Simulation results are provided to further substantiate the validity of the proposed approach to test nanocrossbars of very large dimension and with different switch distribution.